Lines Matching +full:tx +full:- +full:max +full:- +full:burst +full:- +full:prd
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
47 #include <linux/dma-mapping.h>
95 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
97 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
103 * Per-chip ("all ports") interrupt coalescing feature.
133 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
148 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
164 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
165 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
166 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
172 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
173 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
203 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
209 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
216 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
217 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
230 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
231 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
242 * Per-HC (Host-Controller) interrupt coalescing feature.
266 LTMODE = 0x30c, /* requires read-after-write */
272 PHY_MODE4 = 0x314, /* requires read-after-write */
306 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
309 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
311 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
312 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
317 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
323 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
339 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
346 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
397 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
412 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
413 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
425 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
449 * we need on /length/ in mv_fill-sg().
507 * when switching between EDMA and non-EDMA modes.
556 * all the clock operations become no-ops (see clk.h).
568 * alignment for hardware-accessed data structures,
670 .can_queue = MV_MAX_Q_DEPTH - 1,
878 * This is hot-path stuff, so not a function.
922 struct mv_host_priv *hpriv = host->private_data; in mv_host_base()
923 return hpriv->base; in mv_host_base()
928 return mv_port_base(mv_host_base(ap->host), ap->port_no); in mv_ap_base()
937 * mv_save_cached_regs - (re-)initialize cached port registers
949 struct mv_port_priv *pp = ap->private_data; in mv_save_cached_regs()
951 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
952 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
953 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
954 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
958 * mv_write_cached_reg - write to a cached port register
972 * Workaround for 88SX60x1-B2 FEr SATA#13: in mv_write_cached_reg()
973 * Read-after-write is needed to prevent generating 64-bit in mv_write_cached_reg()
978 * +1 usec read-after-write delay for unaffected registers. in mv_write_cached_reg()
1001 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1002 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1004 WARN_ON(pp->crqb_dma & 0x3ff); in mv_set_edma_ptrs()
1005 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
1006 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1013 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1014 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1016 WARN_ON(pp->crpb_dma & 0xff); in mv_set_edma_ptrs()
1017 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); in mv_set_edma_ptrs()
1019 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1037 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1043 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask()
1046 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1049 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1057 unsigned int shift, hardport, port = ap->port_no; in mv_enable_port_irqs()
1064 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); in mv_enable_port_irqs()
1071 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs()
1072 int hardport = mv_hardport_from_port(ap->port_no); in mv_clear_and_enable_port_irqs()
1074 mv_host_base(ap->host), ap->port_no); in mv_clear_and_enable_port_irqs()
1094 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing()
1095 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1098 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1114 spin_lock_irqsave(&host->lock, flags); in mv_set_irq_coalescing()
1150 spin_unlock_irqrestore(&host->lock, flags); in mv_set_irq_coalescing()
1154 * mv_start_edma - Enable eDMA engine
1168 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { in mv_start_edma()
1169 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); in mv_start_edma()
1173 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { in mv_start_edma()
1174 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma()
1182 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; in mv_start_edma()
1197 * with two drives in-use. So we use the 15msec value above in mv_wait_for_edma_empty_idle()
1210 * mv_stop_edma_engine - Disable eDMA engine
1224 for (i = 10000; i > 0; i--) { in mv_stop_edma_engine()
1230 return -EIO; in mv_stop_edma_engine()
1236 struct mv_port_priv *pp = ap->private_data; in mv_stop_edma()
1239 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_stop_edma()
1241 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_stop_edma()
1245 err = -EIO; in mv_stop_edma()
1258 o += snprintf(linebuf + o, sizeof(linebuf) - o, in mv_dump_mem()
1276 o += snprintf(linebuf + o, sizeof(linebuf) - o, in mv_dump_pci_cfg()
1280 dev_dbg(&pdev->dev, "%s: %02x: %s\n", in mv_dump_pci_cfg()
1295 dev_dbg(&pdev->dev, in mv_dump_all_regs()
1296 "%s: All registers for port(s) %u-%u:\n", __func__, in mv_dump_all_regs()
1297 start_port, num_ports > 1 ? num_ports - 1 : start_port); in mv_dump_all_regs()
1299 dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); in mv_dump_all_regs()
1302 dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); in mv_dump_all_regs()
1303 mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); in mv_dump_all_regs()
1304 mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); in mv_dump_all_regs()
1305 mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); in mv_dump_all_regs()
1306 mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); in mv_dump_all_regs()
1309 dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); in mv_dump_all_regs()
1310 mv_dump_mem(&pdev->dev, hc_base, 0x1c); in mv_dump_all_regs()
1314 dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); in mv_dump_all_regs()
1315 mv_dump_mem(&pdev->dev, port_base, 0x54); in mv_dump_all_regs()
1316 dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); in mv_dump_all_regs()
1317 mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); in mv_dump_all_regs()
1346 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1349 return -EINVAL; in mv_scr_read()
1357 void __iomem *addr = mv_ap_base(link->ap) + ofs; in mv_scr_write()
1358 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write()
1376 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1378 mv_ap_base(link->ap) + LP_PHY_CTL; in mv_scr_write()
1398 return -EINVAL; in mv_scr_write()
1404 * Deal with Gen-II ("mv6") hardware quirks/restrictions: in mv6_dev_config()
1406 * Gen-II does not support NCQ over a port multiplier in mv6_dev_config()
1407 * (no FIS-based switching). in mv6_dev_config()
1409 if (adev->flags & ATA_DFLAG_NCQ) { in mv6_dev_config()
1410 if (sata_pmp_attached(adev->link->ap)) { in mv6_dev_config()
1411 adev->flags &= ~ATA_DFLAG_NCQ; in mv6_dev_config()
1413 "NCQ disabled for command-based switching\n"); in mv6_dev_config()
1420 struct ata_link *link = qc->dev->link; in mv_qc_defer()
1421 struct ata_port *ap = link->ap; in mv_qc_defer()
1422 struct mv_port_priv *pp = ap->private_data; in mv_qc_defer()
1426 * for NCQ and/or FIS-based switching. in mv_qc_defer()
1428 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_qc_defer()
1434 * or a non-NCQ command in NCQ mode. in mv_qc_defer()
1439 if (unlikely(ap->excl_link)) { in mv_qc_defer()
1440 if (link == ap->excl_link) { in mv_qc_defer()
1441 if (ap->nr_active_links) in mv_qc_defer()
1443 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in mv_qc_defer()
1452 if (ap->nr_active_links == 0) in mv_qc_defer()
1461 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && in mv_qc_defer()
1462 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { in mv_qc_defer()
1463 if (ata_is_ncq(qc->tf.protocol)) in mv_qc_defer()
1466 ap->excl_link = link; in mv_qc_defer()
1476 struct mv_port_priv *pp = ap->private_data; in mv_config_fbs()
1479 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; in mv_config_fbs()
1480 u32 ltmode, *old_ltmode = &pp->cached.ltmode; in mv_config_fbs()
1481 u32 haltcond, *old_haltcond = &pp->cached.haltcond; in mv_config_fbs()
1505 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25()
1509 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1515 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1519 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1524 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1532 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_enable_iie()
1533 u32 new, *old = &pp->cached.unknown_rsvd; in mv_bmdma_enable_iie()
1558 struct ata_host *host = ap->host; in mv_soc_led_blink_enable()
1559 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable()
1563 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1565 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1566 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_enable()
1573 struct ata_host *host = ap->host; in mv_soc_led_blink_disable()
1574 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable()
1579 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1582 /* disable led-blink only if no ports are using NCQ */ in mv_soc_led_blink_disable()
1583 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1584 struct ata_port *this_ap = host->ports[port]; in mv_soc_led_blink_disable()
1585 struct mv_port_priv *pp = this_ap->private_data; in mv_soc_led_blink_disable()
1587 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_soc_led_blink_disable()
1591 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1592 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_disable()
1600 struct mv_port_priv *pp = ap->private_data; in mv_edma_cfg()
1601 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg()
1604 /* set up non-NCQ EDMA configuration */ in mv_edma_cfg()
1606 pp->pp_flags &= in mv_edma_cfg()
1610 cfg |= (1 << 8); /* enab config burst size mask */ in mv_edma_cfg()
1621 * The chip can use FBS with non-NCQ, if we allow it, in mv_edma_cfg()
1624 * So disallow non-NCQ FBS for now. in mv_edma_cfg()
1631 pp->pp_flags |= MV_PP_FLAG_FBS_EN; in mv_edma_cfg()
1632 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ in mv_edma_cfg()
1637 cfg |= (1 << 22); /* enab 4-entry host queue cache */ in mv_edma_cfg()
1641 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1642 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ in mv_edma_cfg()
1655 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; in mv_edma_cfg()
1663 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem()
1664 struct mv_port_priv *pp = ap->private_data; in mv_port_free_dma_mem()
1667 if (pp->crqb) { in mv_port_free_dma_mem()
1668 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1669 pp->crqb = NULL; in mv_port_free_dma_mem()
1671 if (pp->crpb) { in mv_port_free_dma_mem()
1672 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1673 pp->crpb = NULL; in mv_port_free_dma_mem()
1680 if (pp->sg_tbl[tag]) { in mv_port_free_dma_mem()
1682 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1683 pp->sg_tbl[tag], in mv_port_free_dma_mem()
1684 pp->sg_tbl_dma[tag]); in mv_port_free_dma_mem()
1685 pp->sg_tbl[tag] = NULL; in mv_port_free_dma_mem()
1691 * mv_port_start - Port specific init/start routine.
1702 struct device *dev = ap->host->dev; in mv_port_start()
1703 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start()
1710 return -ENOMEM; in mv_port_start()
1711 ap->private_data = pp; in mv_port_start()
1713 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1714 if (!pp->crqb) in mv_port_start()
1715 return -ENOMEM; in mv_port_start()
1717 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1718 if (!pp->crpb) in mv_port_start()
1722 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1723 ap->flags |= ATA_FLAG_AN; in mv_port_start()
1730 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
1731 GFP_KERNEL, &pp->sg_tbl_dma[tag]); in mv_port_start()
1732 if (!pp->sg_tbl[tag]) in mv_port_start()
1735 pp->sg_tbl[tag] = pp->sg_tbl[0]; in mv_port_start()
1736 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; in mv_port_start()
1740 spin_lock_irqsave(ap->lock, flags); in mv_port_start()
1743 spin_unlock_irqrestore(ap->lock, flags); in mv_port_start()
1749 return -ENOMEM; in mv_port_start()
1753 * mv_port_stop - Port specific cleanup/stop routine.
1765 spin_lock_irqsave(ap->lock, flags); in mv_port_stop()
1768 spin_unlock_irqrestore(ap->lock, flags); in mv_port_stop()
1773 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1783 struct mv_port_priv *pp = qc->ap->private_data; in mv_fill_sg()
1788 mv_sg = pp->sg_tbl[qc->hw_tag]; in mv_fill_sg()
1789 for_each_sg(qc->sg, sg, qc->n_elem, si) { in mv_fill_sg()
1798 len = 0x10000 - offset; in mv_fill_sg()
1800 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); in mv_fill_sg()
1801 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); in mv_fill_sg()
1802 mv_sg->flags_size = cpu_to_le32(len & 0xffff); in mv_fill_sg()
1803 mv_sg->reserved = 0; in mv_fill_sg()
1805 sg_len -= len; in mv_fill_sg()
1814 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); in mv_fill_sg()
1826 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1831 * after libata-sff handles the bmdma interrupts.
1839 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1851 struct scsi_cmnd *scmd = qc->scsicmd; in mv_check_atapi_dma()
1854 switch (scmd->cmnd[0]) { in mv_check_atapi_dma()
1867 return -EOPNOTSUPP; /* use PIO instead */ in mv_check_atapi_dma()
1871 * mv_bmdma_setup - Set up BMDMA transaction
1879 struct ata_port *ap = qc->ap; in mv_bmdma_setup()
1881 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_setup()
1888 /* load PRD table addr. */ in mv_bmdma_setup()
1889 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, in mv_bmdma_setup()
1891 writelfl(pp->sg_tbl_dma[qc->hw_tag], in mv_bmdma_setup()
1895 ap->ops->sff_exec_command(ap, &qc->tf); in mv_bmdma_setup()
1899 * mv_bmdma_start - Start a BMDMA transaction
1907 struct ata_port *ap = qc->ap; in mv_bmdma_start()
1909 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); in mv_bmdma_start()
1917 * mv_bmdma_stop_ap - Stop BMDMA transfer
1936 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ in mv_bmdma_stop_ap()
1943 mv_bmdma_stop_ap(qc->ap); in mv_bmdma_stop()
1947 * mv_bmdma_status - Read BMDMA status
1977 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) in mv_bmdma_status()
1987 struct ata_taskfile *tf = &qc->tf; in mv_rw_multi_errata_sata24()
2001 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { in mv_rw_multi_errata_sata24()
2002 if (qc->dev->multi_count > 7) { in mv_rw_multi_errata_sata24()
2003 switch (tf->command) { in mv_rw_multi_errata_sata24()
2005 tf->command = ATA_CMD_PIO_WRITE; in mv_rw_multi_errata_sata24()
2008 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ in mv_rw_multi_errata_sata24()
2011 tf->command = ATA_CMD_PIO_WRITE_EXT; in mv_rw_multi_errata_sata24()
2019 * mv_qc_prep - Host specific command preparation.
2032 struct ata_port *ap = qc->ap; in mv_qc_prep()
2033 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep()
2035 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep()
2039 switch (tf->protocol) { in mv_qc_prep()
2041 if (tf->command == ATA_CMD_DSM) in mv_qc_prep()
2055 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep()
2057 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep()
2058 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep()
2059 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep()
2062 in_index = pp->req_idx; in mv_qc_prep()
2064 pp->crqb[in_index].sg_addr = in mv_qc_prep()
2065 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep()
2066 pp->crqb[in_index].sg_addr_hi = in mv_qc_prep()
2067 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep()
2068 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); in mv_qc_prep()
2070 cw = &pp->crqb[in_index].ata_cmd[0]; in mv_qc_prep()
2072 /* Sadly, the CRQB cannot accommodate all registers--there are in mv_qc_prep()
2079 switch (tf->command) { in mv_qc_prep()
2085 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2089 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2090 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2093 /* The only other commands EDMA supports in non-queued and in mv_qc_prep()
2094 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none in mv_qc_prep()
2099 tf->command); in mv_qc_prep()
2102 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2103 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2104 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2105 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2106 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2107 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2108 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2109 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); in mv_qc_prep()
2110 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ in mv_qc_prep()
2112 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep()
2120 * mv_qc_prep_iie - Host specific command preparation.
2133 struct ata_port *ap = qc->ap; in mv_qc_prep_iie()
2134 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep_iie()
2136 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep_iie()
2140 if ((tf->protocol != ATA_PROT_DMA) && in mv_qc_prep_iie()
2141 (tf->protocol != ATA_PROT_NCQ)) in mv_qc_prep_iie()
2143 if (tf->command == ATA_CMD_DSM) in mv_qc_prep_iie()
2147 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep_iie()
2150 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep_iie()
2151 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep_iie()
2152 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; in mv_qc_prep_iie()
2153 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep_iie()
2156 in_index = pp->req_idx; in mv_qc_prep_iie()
2158 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; in mv_qc_prep_iie()
2159 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep_iie()
2160 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep_iie()
2161 crqb->flags = cpu_to_le32(flags); in mv_qc_prep_iie()
2163 crqb->ata_cmd[0] = cpu_to_le32( in mv_qc_prep_iie()
2164 (tf->command << 16) | in mv_qc_prep_iie()
2165 (tf->feature << 24) in mv_qc_prep_iie()
2167 crqb->ata_cmd[1] = cpu_to_le32( in mv_qc_prep_iie()
2168 (tf->lbal << 0) | in mv_qc_prep_iie()
2169 (tf->lbam << 8) | in mv_qc_prep_iie()
2170 (tf->lbah << 16) | in mv_qc_prep_iie()
2171 (tf->device << 24) in mv_qc_prep_iie()
2173 crqb->ata_cmd[2] = cpu_to_le32( in mv_qc_prep_iie()
2174 (tf->hob_lbal << 0) | in mv_qc_prep_iie()
2175 (tf->hob_lbam << 8) | in mv_qc_prep_iie()
2176 (tf->hob_lbah << 16) | in mv_qc_prep_iie()
2177 (tf->hob_feature << 24) in mv_qc_prep_iie()
2179 crqb->ata_cmd[3] = cpu_to_le32( in mv_qc_prep_iie()
2180 (tf->nsect << 0) | in mv_qc_prep_iie()
2181 (tf->hob_nsect << 8) in mv_qc_prep_iie()
2184 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep_iie()
2192 * mv_sff_check_status - fetch device status, if valid
2206 u8 stat = ioread8(ap->ioaddr.status_addr); in mv_sff_check_status()
2207 struct mv_port_priv *pp = ap->private_data; in mv_sff_check_status()
2209 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { in mv_sff_check_status()
2211 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; in mv_sff_check_status()
2219 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2222 * @nwords: number of 32-bit words in the fis
2228 int i, timeout = 200, final_word = nwords - 1; in mv_send_fis()
2239 /* Flag end-of-transmission, and then send the final word */ in mv_send_fis()
2249 } while (!(ifstat & 0x1000) && --timeout); in mv_send_fis()
2264 * mv_qc_issue_fis - Issue a command directly as a FIS
2274 * of non-data commands. So avoid sending them via this function,
2282 struct ata_port *ap = qc->ap; in mv_qc_issue_fis()
2283 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue_fis()
2284 struct ata_link *link = qc->dev->link; in mv_qc_issue_fis()
2288 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); in mv_qc_issue_fis()
2293 switch (qc->tf.protocol) { in mv_qc_issue_fis()
2295 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2298 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2301 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2302 if (qc->tf.flags & ATA_TFLAG_WRITE) in mv_qc_issue_fis()
2303 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2305 ap->hsm_task_state = HSM_ST; in mv_qc_issue_fis()
2308 ap->hsm_task_state = HSM_ST_LAST; in mv_qc_issue_fis()
2312 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue_fis()
2318 * mv_qc_issue - Initiate a command to the host
2332 struct ata_port *ap = qc->ap; in mv_qc_issue()
2334 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue()
2338 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ in mv_qc_issue()
2340 switch (qc->tf.protocol) { in mv_qc_issue()
2342 if (qc->tf.command == ATA_CMD_DSM) { in mv_qc_issue()
2343 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ in mv_qc_issue()
2349 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); in mv_qc_issue()
2350 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_qc_issue()
2351 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_qc_issue()
2354 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, in mv_qc_issue()
2370 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { in mv_qc_issue()
2371 --limit_warnings; in mv_qc_issue()
2372 ata_link_warn(qc->dev->link, DRV_NAME in mv_qc_issue()
2380 if (ap->flags & ATA_FLAG_PIO_POLLING) in mv_qc_issue()
2381 qc->tf.flags |= ATA_TFLAG_POLLING; in mv_qc_issue()
2385 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue()
2391 * We're about to send a non-EDMA capable command to the in mv_qc_issue()
2397 mv_pmp_select(ap, qc->dev->link->pmp); in mv_qc_issue()
2399 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { in mv_qc_issue()
2400 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue()
2405 * from libata-eh *must* use mv_qc_issue_fis(). in mv_qc_issue()
2408 * Rather than special-case it, we'll just *always* in mv_qc_issue()
2420 struct mv_port_priv *pp = ap->private_data; in mv_get_active_qc()
2423 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_get_active_qc()
2425 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_get_active_qc()
2426 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) in mv_get_active_qc()
2434 struct mv_port_priv *pp = ap->private_data; in mv_pmp_error_handler()
2436 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { in mv_pmp_error_handler()
2443 pmp_map = pp->delayed_eh_pmp_map; in mv_pmp_error_handler()
2444 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; in mv_pmp_error_handler()
2448 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_error_handler()
2475 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_eh_prep()
2476 struct ata_eh_info *ehi = &link->eh_info; in mv_pmp_eh_prep()
2481 ehi->err_mask |= AC_ERR_DEV; in mv_pmp_eh_prep()
2482 ehi->action |= ATA_EH_RESET; in mv_pmp_eh_prep()
2502 struct mv_port_priv *pp = ap->private_data; in mv_handle_fbs_ncq_dev_err()
2511 * Perform the post-mortem/EH only when all responses are complete. in mv_handle_fbs_ncq_dev_err()
2514 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { in mv_handle_fbs_ncq_dev_err()
2515 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; in mv_handle_fbs_ncq_dev_err()
2516 pp->delayed_eh_pmp_map = 0; in mv_handle_fbs_ncq_dev_err()
2518 old_map = pp->delayed_eh_pmp_map; in mv_handle_fbs_ncq_dev_err()
2522 pp->delayed_eh_pmp_map = new_map; in mv_handle_fbs_ncq_dev_err()
2529 __func__, pp->delayed_eh_pmp_map, in mv_handle_fbs_ncq_dev_err()
2530 ap->qc_active, failed_links, in mv_handle_fbs_ncq_dev_err()
2531 ap->nr_active_links); in mv_handle_fbs_ncq_dev_err()
2533 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { in mv_handle_fbs_ncq_dev_err()
2549 * FBS+non-NCQ operation is not yet implemented. in mv_handle_fbs_non_ncq_dev_err()
2552 * Device error during FBS+non-NCQ operation: in mv_handle_fbs_non_ncq_dev_err()
2562 struct mv_port_priv *pp = ap->private_data; in mv_handle_dev_err()
2564 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_handle_dev_err()
2566 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) in mv_handle_dev_err()
2575 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { in mv_handle_dev_err()
2577 * EDMA should NOT have self-disabled for this case. in mv_handle_dev_err()
2583 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2589 * EDMA should have self-disabled for this case. in mv_handle_dev_err()
2595 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2605 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_unexpected_intr()
2612 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_unexpected_intr()
2613 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) in mv_unexpected_intr()
2617 ehi->err_mask |= AC_ERR_OTHER; in mv_unexpected_intr()
2618 ehi->action |= ATA_EH_RESET; in mv_unexpected_intr()
2623 * mv_err_intr - Handle error interrupts on the port
2638 struct mv_port_priv *pp = ap->private_data; in mv_err_intr()
2639 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr()
2641 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_err_intr()
2650 sata_scr_read(&ap->link, SCR_ERROR, &serr); in mv_err_intr()
2651 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); in mv_err_intr()
2662 * Device errors during FIS-based switching operation in mv_err_intr()
2672 edma_err_cause, pp->pp_flags); in mv_err_intr()
2708 * Gen-I has a different SELF_DIS bit, in mv_err_intr()
2714 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2715 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2720 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2721 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2735 ehi->serror |= serr; in mv_err_intr()
2736 ehi->action |= action; in mv_err_intr()
2739 qc->err_mask |= err_mask; in mv_err_intr()
2741 ehi->err_mask |= err_mask; in mv_err_intr()
2762 ata_link_abort(qc->dev->link); in mv_err_intr()
2772 u16 edma_status = le16_to_cpu(response->flags); in mv_process_crpb_response()
2776 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). in mv_process_crpb_response()
2799 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries()
2803 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); in mv_process_crpb_entries()
2810 while (in_index != pp->resp_idx) { in mv_process_crpb_entries()
2812 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; in mv_process_crpb_entries()
2814 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_process_crpb_entries()
2818 tag = ap->link.active_tag; in mv_process_crpb_entries()
2821 tag = le16_to_cpu(response->id) & 0x1f; in mv_process_crpb_entries()
2832 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | in mv_process_crpb_entries()
2833 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), in mv_process_crpb_entries()
2848 pp = ap->private_data; in mv_port_intr()
2849 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); in mv_port_intr()
2855 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_port_intr()
2859 * Handle chip-reported errors, or continue on to handle PIO. in mv_port_intr()
2873 * mv_host_intr - Handle all interrupts on the given host controller
2882 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr()
2883 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2890 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2891 struct ata_port *ap = host->ports[port]; in mv_host_intr()
2906 port += MV_PORTS_PER_HC - 1; in mv_host_intr()
2925 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2947 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error()
2954 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2956 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); in mv_pci_error()
2958 dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); in mv_pci_error()
2959 mv_dump_all_regs(mmio, to_pci_dev(host->dev)); in mv_pci_error()
2961 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
2963 for (i = 0; i < host->n_ports; i++) { in mv_pci_error()
2964 ap = host->ports[i]; in mv_pci_error()
2965 if (!ata_link_offline(&ap->link)) { in mv_pci_error()
2966 ehi = &ap->link.eh_info; in mv_pci_error()
2972 ehi->action = ATA_EH_RESET; in mv_pci_error()
2973 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_pci_error()
2975 qc->err_mask |= err_mask; in mv_pci_error()
2977 ehi->err_mask |= err_mask; in mv_pci_error()
2986 * mv_interrupt - Main interrupt event handler
3002 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt()
3004 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3007 spin_lock(&host->lock); in mv_interrupt()
3013 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3014 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3021 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3028 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3030 spin_unlock(&host->lock); in mv_interrupt()
3054 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read()
3055 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3056 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_read()
3063 return -EINVAL; in mv5_scr_read()
3068 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write()
3069 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3070 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_write()
3077 return -EINVAL; in mv5_scr_write()
3082 struct pci_dev *pdev = to_pci_dev(host->dev); in mv5_reset_bus()
3085 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); in mv5_reset_bus()
3109 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3110 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3132 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3147 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3148 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3200 struct mv_host_priv *hpriv = host->private_data; in mv5_reset_hc()
3218 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus()
3229 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3230 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3251 * mv6_reset_hc - Perform the 6xxx global soft reset
3279 dev_err(host->dev, "PCI master won't flush\n"); in mv6_reset_hc()
3290 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3293 dev_err(host->dev, "can't set global reset\n"); in mv6_reset_hc()
3304 } while ((GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3307 dev_err(host->dev, "can't clear global reset\n"); in mv6_reset_hc()
3322 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3323 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3330 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3331 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3344 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3367 * Gen-II/IIe PHY_MODE3 errata RM#2: in mv6_phy_errata()
3373 /* Guideline 88F5182 (GL# SATA-S11) */ in mv6_phy_errata()
3380 * Enforce reserved-bit restrictions on GenIIe devices only. in mv6_phy_errata()
3391 * Workaround for 60x1-B2 errata SATA#13: in mv6_phy_errata()
3398 /* Revert values of pre-emphasis and signal amps to the saved ones */ in mv6_phy_errata()
3402 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3403 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3432 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3433 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3479 struct mv_host_priv *hpriv = host->private_data; in mv_soc_reset_hc()
3482 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3533 * soc_is_65 - check if the soc is 65 nano device
3536 * register, this register should contain non-zero value and it exists only
3541 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3584 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3607 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_pmp_hardreset()
3614 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_softreset()
3621 struct ata_port *ap = link->ap; in mv_hardreset()
3622 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset()
3623 struct mv_port_priv *pp = ap->private_data; in mv_hardreset()
3624 void __iomem *mmio = hpriv->base; in mv_hardreset()
3629 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3630 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_hardreset()
3631 pp->pp_flags &= in mv_hardreset()
3637 sata_ehc_deb_timing(&link->eh_context); in mv_hardreset()
3641 rc = online ? -EAGAIN : rc; in mv_hardreset()
3649 extra = HZ; /* only extend it once, max */ in mv_hardreset()
3666 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw()
3667 unsigned int port = ap->port_no; in mv_eh_thaw()
3669 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3684 * mv_port_init - Perform some early initialization on a single port.
3701 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); in mv_port_init()
3702 port->error_addr = in mv_port_init()
3703 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); in mv_port_init()
3704 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); in mv_port_init()
3705 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); in mv_port_init()
3706 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); in mv_port_init()
3707 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); in mv_port_init()
3708 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); in mv_port_init()
3709 port->status_addr = in mv_port_init()
3710 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); in mv_port_init()
3712 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; in mv_port_init()
3719 /* unmask all non-transient EDMA error interrupts */ in mv_port_init()
3725 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode()
3726 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3730 return 0; /* not PCI-X capable */ in mv_in_pcix_mode()
3734 return 1; /* chip is in PCI-X mode */ in mv_in_pcix_mode()
3739 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay()
3740 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3753 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7()
3754 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3756 /* workaround for 60x1-B2 errata PCI#7 */ in mv_60x1b2_errata_pci7()
3765 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_chip_id()
3766 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id()
3767 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3771 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3774 switch (pdev->revision) { in mv_chip_id()
3782 dev_warn(&pdev->dev, in mv_chip_id()
3791 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3794 switch (pdev->revision) { in mv_chip_id()
3802 dev_warn(&pdev->dev, in mv_chip_id()
3811 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3814 switch (pdev->revision) { in mv_chip_id()
3823 dev_warn(&pdev->dev, in mv_chip_id()
3832 if (pdev->vendor == PCI_VENDOR_ID_TTI && in mv_chip_id()
3833 (pdev->device == 0x2300 || pdev->device == 0x2310)) in mv_chip_id()
3848 * RAID metadata is at: (dev->n_sectors & ~0xfffff) in mv_chip_id()
3852 dev_warn(&pdev->dev, "Highpoint RocketRAID" in mv_chip_id()
3856 dev_warn(&pdev->dev, "For data safety, do not" in mv_chip_id()
3857 " use sectors 8-9 on \"Legacy\" drives," in mv_chip_id()
3863 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3868 switch (pdev->revision) { in mv_chip_id()
3873 dev_warn(&pdev->dev, in mv_chip_id()
3881 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3883 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3889 dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx); in mv_chip_id()
3890 return -EINVAL; in mv_chip_id()
3893 hpriv->hp_flags = hp_flags; in mv_chip_id()
3895 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3896 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3897 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3899 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3900 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3901 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3908 * mv_init_host - Perform some early initialization of the host.
3920 struct mv_host_priv *hpriv = host->private_data; in mv_init_host()
3921 void __iomem *mmio = hpriv->base; in mv_init_host()
3923 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3928 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3929 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3931 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3932 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3936 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3941 n_hc = mv_get_hc_count(host->ports[0]->flags); in mv_init_host()
3943 for (port = 0; port < host->n_ports; port++) in mv_init_host()
3944 if (hpriv->ops->read_preamp) in mv_init_host()
3945 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3947 rc = hpriv->ops->reset_hc(host, mmio, n_hc); in mv_init_host()
3951 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3952 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3953 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3955 for (port = 0; port < host->n_ports; port++) { in mv_init_host()
3956 struct ata_port *ap = host->ports[port]; in mv_init_host()
3959 mv_port_init(&ap->ioaddr, port_mmio); in mv_init_host()
3965 dev_dbg(host->dev, "HC%i: HC config=0x%08x HC IRQ cause " in mv_init_host()
3976 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3979 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
3984 * The per-port interrupts get done later as ports are set up. in mv_init_host()
3995 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
3997 if (!hpriv->crqb_pool) in mv_create_dma_pools()
3998 return -ENOMEM; in mv_create_dma_pools()
4000 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4002 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4003 return -ENOMEM; in mv_create_dma_pools()
4005 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4007 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4008 return -ENOMEM; in mv_create_dma_pools()
4019 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4020 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4023 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
4024 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
4026 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
4027 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
4028 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
4029 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4030 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4035 * mv_platform_probe - handle a positive probe of an soc Marvell
4055 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_platform_probe()
4060 if (unlikely(pdev->num_resources != 1)) { in mv_platform_probe()
4061 dev_err(&pdev->dev, "invalid number of resources\n"); in mv_platform_probe()
4062 return -EINVAL; in mv_platform_probe()
4070 return -EINVAL; in mv_platform_probe()
4073 if (pdev->dev.of_node) { in mv_platform_probe()
4074 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", in mv_platform_probe()
4077 dev_err(&pdev->dev, in mv_platform_probe()
4078 "error parsing nr-ports property: %d\n", rc); in mv_platform_probe()
4083 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", in mv_platform_probe()
4085 return -EINVAL; in mv_platform_probe()
4088 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in mv_platform_probe()
4090 mv_platform_data = dev_get_platdata(&pdev->dev); in mv_platform_probe()
4091 n_ports = mv_platform_data->n_ports; in mv_platform_probe()
4097 return -EINVAL; in mv_platform_probe()
4099 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_platform_probe()
4100 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4103 return -ENOMEM; in mv_platform_probe()
4104 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4107 if (!hpriv->port_clks) in mv_platform_probe()
4108 return -ENOMEM; in mv_platform_probe()
4109 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4112 if (!hpriv->port_phys) in mv_platform_probe()
4113 return -ENOMEM; in mv_platform_probe()
4114 host->private_data = hpriv; in mv_platform_probe()
4115 hpriv->board_idx = chip_soc; in mv_platform_probe()
4117 host->iomap = NULL; in mv_platform_probe()
4118 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4120 if (!hpriv->base) in mv_platform_probe()
4121 return -ENOMEM; in mv_platform_probe()
4123 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4125 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4126 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4127 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); in mv_platform_probe()
4129 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4134 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4135 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4136 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4139 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4141 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4142 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4143 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4144 if (rc != -EPROBE_DEFER) in mv_platform_probe()
4145 dev_warn(&pdev->dev, "error getting phy %d", rc); in mv_platform_probe()
4148 hpriv->n_ports = port; in mv_platform_probe()
4151 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4155 hpriv->n_ports = n_ports; in mv_platform_probe()
4158 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_probe()
4164 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4172 if (pdev->dev.of_node && in mv_platform_probe()
4173 of_device_is_compatible(pdev->dev.of_node, in mv_platform_probe()
4174 "marvell,armada-370-sata")) in mv_platform_probe()
4175 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4182 dev_info(&pdev->dev, "slots %u ports %d\n", in mv_platform_probe()
4183 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); in mv_platform_probe()
4190 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4191 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4192 clk_put(hpriv->clk); in mv_platform_probe()
4194 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4195 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4196 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4197 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4199 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4207 * mv_platform_remove - unplug a platform interface
4216 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove()
4220 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4221 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4222 clk_put(hpriv->clk); in mv_platform_remove()
4224 for (port = 0; port < host->n_ports; port++) { in mv_platform_remove()
4225 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4226 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4227 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4229 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4251 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume()
4254 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_resume()
4263 dev_err(&pdev->dev, "Error during HW init\n"); in mv_platform_resume()
4278 { .compatible = "marvell,armada-370-sata", },
4279 { .compatible = "marvell,orion-sata", },
4318 * mv_print_info - Dump key info to kernel log for perusal.
4328 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_print_info()
4329 struct mv_host_priv *hpriv = host->private_data; in mv_print_info()
4353 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", in mv_print_info()
4354 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, in mv_print_info()
4355 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4359 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4369 unsigned int board_idx = (unsigned int)ent->driver_data; in mv_pci_init_one()
4375 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_pci_init_one()
4378 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; in mv_pci_init_one()
4380 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_pci_init_one()
4381 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4383 return -ENOMEM; in mv_pci_init_one()
4384 host->private_data = hpriv; in mv_pci_init_one()
4385 hpriv->n_ports = n_ports; in mv_pci_init_one()
4386 hpriv->board_idx = board_idx; in mv_pci_init_one()
4394 if (rc == -EBUSY) in mv_pci_init_one()
4398 host->iomap = pcim_iomap_table(pdev); in mv_pci_init_one()
4399 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4401 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in mv_pci_init_one()
4403 dev_err(&pdev->dev, "DMA enable failed\n"); in mv_pci_init_one()
4407 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4411 for (port = 0; port < host->n_ports; port++) { in mv_pci_init_one()
4412 struct ata_port *ap = host->ports[port]; in mv_pci_init_one()
4413 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4414 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4416 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); in mv_pci_init_one()
4425 /* Enable message-switched interrupts, if requested */ in mv_pci_init_one()
4427 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4434 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, in mv_pci_init_one()
4462 int rc = -ENODEV; in mv_init()
4486 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");