214 static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)  in __combo_phy_reg_read()  argument
217 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_read()
219 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_read()
220 	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_read()
225 static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)  in __combo_phy_reg_write()  argument
227 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_write()
229 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_write()
230 	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_write()
234 static void combo_phy_wait_for_ready(u8 sata_port)  in combo_phy_wait_for_ready()  argument
236 	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)  in combo_phy_wait_for_ready()
240 static u32 combo_phy_read(u8 sata_port, u32 addr)  in combo_phy_read()  argument
242 	combo_phy_wait_for_ready(sata_port);  in combo_phy_read()
243 	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);  in combo_phy_read()
244 	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);  in combo_phy_read()
245 	combo_phy_wait_for_ready(sata_port);  in combo_phy_read()
246 	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);  in combo_phy_read()
249 static void combo_phy_write(u8 sata_port, u32 addr, u32 data)  in combo_phy_write()  argument
251 	combo_phy_wait_for_ready(sata_port);  in combo_phy_write()
252 	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);  in combo_phy_write()
253 	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);  in combo_phy_write()
254 	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);  in combo_phy_write()
257 static void highbank_cphy_disable_overrides(u8 sata_port)  in highbank_cphy_disable_overrides()  argument
259 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_disable_overrides()
261 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_disable_overrides()
263 	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);  in highbank_cphy_disable_overrides()
265 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in highbank_cphy_disable_overrides()
268 static void cphy_override_tx_attenuation(u8 sata_port, u32 val)  in cphy_override_tx_attenuation()  argument
270 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_tx_attenuation()
276 	tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);  in cphy_override_tx_attenuation()
278 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
281 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
284 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
287 static void cphy_override_rx_mode(u8 sata_port, u32 val)  in cphy_override_rx_mode()  argument
289 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_rx_mode()
291 	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);  in cphy_override_rx_mode()
293 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
296 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
300 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
303 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
306 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
311 static void highbank_cphy_override_lane(u8 sata_port)  in highbank_cphy_override_lane()  argument
313 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_override_lane()
316 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_override_lane()
319 		tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +  in highbank_cphy_override_lane()
322 	cphy_override_rx_mode(sata_port, 3);  in highbank_cphy_override_lane()
323 	cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);  in highbank_cphy_override_lane()