Lines Matching full:timings
10 * slave timings, SITRE or PPE. In that sense it is a close relative
12 * although no other modes/timings. Also lacking is 32bit I/O on the ATA
30 * radisys_set_piomode - Initialize host controller PATA PIO timings
32 * @adev: Device whose timings we are configuring
55 u8 timings[][2] = { { 0, 0 }, /* Check me */ in radisys_set_piomode() local
72 idetm_data |= (timings[pio][0] << 12) | in radisys_set_piomode()
73 (timings[pio][1] << 8); in radisys_set_piomode()
81 * radisys_set_dmamode - Initialize host controller PATA DMA timings
82 * @ap: Port whose timings we are configuring
98 u8 timings[][2] = { { 0, 0 }, in radisys_set_dmamode() local
105 * MWDMA is driven by the PIO timings. We must also enable in radisys_set_dmamode()
131 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); in radisys_set_dmamode()
162 * this interface so that we can load the correct ATA timings if