20  *		0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21  *		Virtual DMA registers *move* between rev 0x02 and rev 0x10
38 	READ_REG	= 0,	/* index of Read cycle timing register */
45 static int pci_clock;	/* 0 = 33 1 = 25 */
60 		0x40, 1, 0x08, 0x00  in optidma_pre_reset()
99 	iowrite8(0x83, regio + 2);  in optidma_lock()
126 		{ 0x30, 0x20, 0x20, 0x10, 0x10 },  in optidma_mode_setup()
127 		{ 0x20, 0x20, 0x10, 0x10, 0x10 }  in optidma_mode_setup()
130 		{ 0x59, 0x46, 0x30, 0x20, 0x20 },  in optidma_mode_setup()
131 		{ 0x46, 0x32, 0x20, 0x20, 0x10 }  in optidma_mode_setup()
134 		{ 0x76, 0x20, 0x20 },  in optidma_mode_setup()
135 		{ 0x54, 0x20, 0x10 }  in optidma_mode_setup()
149 		addr = 0;  in optidma_mode_setup()
157 			pair_addr = 0;  in optidma_mode_setup()
178 	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */  in optidma_mode_setup()
179 	iowrite8(0x85, regio + CNTRL_REG);  in optidma_mode_setup()
185 	   not supposed to program PCI 0x43 "things we hacked onto the chip"  in optidma_mode_setup()
210 	pci_read_config_byte(pdev, 0x44, &udcfg);  in optiplus_mode_setup()
217 			pci_read_config_byte(pdev, 0x45, &udslave);  in optiplus_mode_setup()
218 			udslave &= ~(0x03 << dev2);  in optiplus_mode_setup()
220 			pci_write_config_byte(pdev, 0x45, udslave);  in optiplus_mode_setup()
222 			udcfg &= ~(0x30 << dev2);  in optiplus_mode_setup()
226 	pci_write_config_byte(pdev, 0x44, udcfg);  in optiplus_mode_setup()
294  *	for register 0x43 and return the two bits needed.
300 		0, 0, 0, 1, 2  in optidma_make_bits43()
303 		return 0;  in optidma_make_bits43()
326 	if (rc == 0) {  in optidma_set_mode()
327 		pci_read_config_byte(pdev, 0x43, &r);  in optidma_set_mode()
329 		r &= (0x0F << nybble);  in optidma_set_mode()
330 		r |= (optidma_make_bits43(&link->device[0]) +  in optidma_set_mode()
331 		     (optidma_make_bits43(&link->device[0]) << 2)) << nybble;  in optidma_set_mode()
332 		pci_write_config_byte(pdev, 0x43, r);  in optidma_set_mode()
364 	int ret = 0;  in optiplus_with_udma()
365 	int ioport = 0x22;  in optiplus_with_udma()
369 	dev1 = pci_get_device(0x1045, 0xC701, NULL);  in optiplus_with_udma()
371 		return 0;  in optiplus_with_udma()
373 	/* Rev must be >= 0x10 */  in optiplus_with_udma()
374 	pci_read_config_byte(dev1, 0x08, &r);  in optiplus_with_udma()
375 	if (r < 0x10)  in optiplus_with_udma()
378 	pci_read_config_byte(dev1, 0x5F, &r);  in optiplus_with_udma()
380 	outb(0x10, ioport);  in optiplus_with_udma()
382 	if ((inb(ioport + 2) & 1) == 0)  in optiplus_with_udma()
386 	pci_read_config_byte(pdev, 0x42, &r);  in optiplus_with_udma()
387 	if ((r & 0x36) != 0x36)  in optiplus_with_udma()
389 	pci_read_config_byte(dev1, 0x52, &r);  in optiplus_with_udma()
390 	if (r & 0x80)	/* IDEDIR disabled */  in optiplus_with_udma()
424 	inw(0x1F1);  in optidma_init_one()
425 	inw(0x1F1);  in optidma_init_one()
426 	pci_clock = inb(0x1F5) & 1;		/* 0 = 33Mhz, 1 = 25Mhz */  in optidma_init_one()
429 		ppi[0] = &info_82c700_udma;  in optidma_init_one()
431 	return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);  in optidma_init_one()
435 	{ PCI_VDEVICE(OPTI, 0xD568), },		/* Opti 82C700 */