1 // SPDX-License-Identifier: GPL-2.0-only
3  * Suspend support specific for i386/x86-64.
40 	struct saved_msr *msr = ctxt->saved_msrs.array;  in msr_save_context()
41 	struct saved_msr *end = msr + ctxt->saved_msrs.num;  in msr_save_context()
44 		if (msr->valid)  in msr_save_context()
45 			rdmsrl(msr->info.msr_no, msr->info.reg.q);  in msr_save_context()
52 	struct saved_msr *msr = ctxt->saved_msrs.array;  in msr_restore_context()
53 	struct saved_msr *end = msr + ctxt->saved_msrs.num;  in msr_restore_context()
56 		if (msr->valid)  in msr_restore_context()
57 			wrmsrl(msr->info.msr_no, msr->info.reg.q);  in msr_restore_context()
63  * __save_processor_state() - Save CPU registers before creating a
64  *                             hibernation image and before restoring
69  * boot kernel (ie. the kernel used for loading the hibernation image)
71  * saved in the hibernation image), then its contents must be saved by this
73  * kernel B is used for loading the hibernation image into memory, the
88 	store_idt(&ctxt->idt);  in __save_processor_state()
92 	 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit  in __save_processor_state()
93 	 * mode in "secondary_startup_64". In 32-bit mode it is done via  in __save_processor_state()
96 	ctxt->gdt_desc.size = GDT_SIZE - 1;  in __save_processor_state()
97 	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());  in __save_processor_state()
99 	store_tr(ctxt->tr);  in __save_processor_state()
105 	savesegment(gs, ctxt->gs);  in __save_processor_state()
107 	savesegment(fs, ctxt->fs);  in __save_processor_state()
108 	savesegment(ds, ctxt->ds);  in __save_processor_state()
109 	savesegment(es, ctxt->es);  in __save_processor_state()
111 	rdmsrl(MSR_FS_BASE, ctxt->fs_base);  in __save_processor_state()
112 	rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);  in __save_processor_state()
113 	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);  in __save_processor_state()
116 	rdmsrl(MSR_EFER, ctxt->efer);  in __save_processor_state()
122 	ctxt->cr0 = read_cr0();  in __save_processor_state()
123 	ctxt->cr2 = read_cr2();  in __save_processor_state()
124 	ctxt->cr3 = __read_cr3();  in __save_processor_state()
125 	ctxt->cr4 = __read_cr4();  in __save_processor_state()
126 	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,  in __save_processor_state()
127 					       &ctxt->misc_enable);  in __save_processor_state()
164 	set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);  in fix_processor_context()
168 	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */  in fix_processor_context()
177 	load_mm_ldt(current->active_mm);	/* This does lldt */  in fix_processor_context()
187  * __restore_processor_state() - Restore the contents of CPU registers saved
198 	if (ctxt->misc_enable_saved)  in __restore_processor_state()
199 		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);  in __restore_processor_state()
205 	if (ctxt->cr4)  in __restore_processor_state()
206 		__write_cr4(ctxt->cr4);  in __restore_processor_state()
209 	wrmsrl(MSR_EFER, ctxt->efer);  in __restore_processor_state()
210 	__write_cr4(ctxt->cr4);  in __restore_processor_state()
212 	write_cr3(ctxt->cr3);  in __restore_processor_state()
213 	write_cr2(ctxt->cr2);  in __restore_processor_state()
214 	write_cr0(ctxt->cr0);  in __restore_processor_state()
217 	load_idt(&ctxt->idt);  in __restore_processor_state()
232 	wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);  in __restore_processor_state()
237 	/* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */  in __restore_processor_state()
245 	loadsegment(ds, ctxt->es);  in __restore_processor_state()
246 	loadsegment(es, ctxt->es);  in __restore_processor_state()
247 	loadsegment(fs, ctxt->fs);  in __restore_processor_state()
248 	load_gs_index(ctxt->gs);  in __restore_processor_state()
255 	wrmsrl(MSR_FS_BASE, ctxt->fs_base);  in __restore_processor_state()
256 	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);  in __restore_processor_state()
258 	loadsegment(gs, ctxt->gs);  in __restore_processor_state()
314 	 * Those will be put to proper (not interfering with hibernation  in hibernate_resume_nonboot_cpu_disable()
337 		return -ENODEV;  in bsp_check()
356 		 * When system resumes from hibernation, online CPU0 because  in bsp_pm_callback()
358 		 * 2. the CPU was online before hibernation  in bsp_pm_callback()
367 		 * This code is called only when user space hibernation software  in bsp_pm_callback()
373 		 * mode, i.e. CPU0 is offline and user mode hibernation  in bsp_pm_callback()
401 	 * earlier to disable cpu hotplug before bsp online check.  in bsp_pm_check_init()
403 	pm_notifier(bsp_pm_callback, -INT_MAX);  in bsp_pm_check_init()
416 	total_num = saved_msrs->num + num;  in msr_build_context()
421 		return -ENOMEM;  in msr_build_context()
424 	if (saved_msrs->array) {  in msr_build_context()
429 		memcpy(msr_array, saved_msrs->array,  in msr_build_context()
430 		       sizeof(struct saved_msr) * saved_msrs->num);  in msr_build_context()
432 		kfree(saved_msrs->array);  in msr_build_context()
435 	for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {  in msr_build_context()
442 	saved_msrs->num   = total_num;  in msr_build_context()
443 	saved_msrs->array = msr_array;  in msr_build_context()
463 	pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);  in msr_initialize_bdw()
473 		DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
486 		c->family);  in msr_save_cpuid_features()
507 		fn = (pm_cpu_match_t)m->driver_data;  in pm_cpu_check()