1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/nospec-branch.h>
35  *	TLB flushing, formerly SMP-only
66  * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
73  * ASID  - [0, TLB_NR_DYN_ASIDS-1]
76  * kPCID - [1, TLB_NR_DYN_ASIDS]
80  * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
100 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
103  * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
104  * for them being zero-based.  Another -1 is because PCID 0 is reserved for
105  * use by non-PCID-aware users.
107 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
130 	 * The dynamically-assigned ASIDs that get passed in are small  in kern_pcid()
134 	 * If PCID is on, ASID-aware code paths put the ASID+1 into the  in kern_pcid()
136 	 * situation in which PCID-unaware code saves CR3, loads some other  in kern_pcid()
138 	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means  in kern_pcid()
139 	 * that any bugs involving loading a PCID-enabled CR3 with  in kern_pcid()
180  * We get here when we do something requiring a TLB invalidation
183  * forces a TLB flush when the context is loaded.
230 		    next->context.ctx_id)  in choose_new_asid()
243 	*new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;  in choose_new_asid()
290 	 * that load_cr3() is serializing and orders TLB  in load_new_mm_cr3()
301 	 * It's plausible that we're in lazy TLB mode while our mm is init_mm.  in leave_mm()
302 	 * If so, our callers still expect us to flush the TLB, but there  in leave_mm()
303 	 * aren't any user TLB entries in init_mm to worry about.  in leave_mm()
329  * Invoked from return to user/guest by a task that opted-in to L1D
357 		clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_evaluate()
358 		next->l1d_flush_kill.func = l1d_flush_force_sigbus;  in l1d_flush_evaluate()
359 		task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);  in l1d_flush_evaluate()
374 	return (unsigned long)next->mm | spec_bits;  in mm_mangle_tif_spec_bits()
381 	if (!next || !next->mm)  in cond_mitigation()
390 	 * doing Spectre-v2 attacks on another.  in cond_mitigation()
394 	 * same process. Using the mm pointer instead of mm->context.ctx_id  in cond_mitigation()
417 		 * - the same user space task is scheduled out and later  in cond_mitigation()
421 		 * - a user space task belonging to the same process is  in cond_mitigation()
424 		 * - a user space task belonging to the same process is  in cond_mitigation()
447 					(unsigned long)next->mm)  in cond_mitigation()
469 	     atomic_read(&mm->context.perf_rdpmc_allowed))) {  in cr4_update_pce_mm()
502 	 * from lazy TLB mode to normal mode if active_mm isn't changing.  in switch_mm_irqs_off()
523 	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {  in switch_mm_irqs_off()
525 		 * If we were to BUG here, we'd be very likely to kill  in switch_mm_irqs_off()
544 	 * core serialization before returning to user-space, after  in switch_mm_irqs_off()
545 	 * storing to rq->curr, when changing mm.  This is because  in switch_mm_irqs_off()
556 			   next->context.ctx_id);  in switch_mm_irqs_off()
559 		 * Even in lazy TLB mode, the CPU should stay set in the  in switch_mm_irqs_off()
560 		 * mm_cpumask. The TLB shootdown code can figure out from  in switch_mm_irqs_off()
568 		 * If the CPU is not in lazy TLB mode, we are just switching  in switch_mm_irqs_off()
570 		 * process. No TLB flush required.  in switch_mm_irqs_off()
577 		 * If the TLB is up to date, just use it.  in switch_mm_irqs_off()
579 		 * the TLB shootdown code.  in switch_mm_irqs_off()
582 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
588 		 * TLB contents went out of date while we were in lazy  in switch_mm_irqs_off()
589 		 * mode. Fall through to the TLB switching code below.  in switch_mm_irqs_off()
602 		 * Skip kernel threads; we never send init_mm TLB flushing IPIs,  in switch_mm_irqs_off()
616 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
626 		this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);  in switch_mm_irqs_off()
628 		load_new_mm_cr3(next->pgd, new_asid, true);  in switch_mm_irqs_off()
633 		load_new_mm_cr3(next->pgd, new_asid, false);  in switch_mm_irqs_off()
657  * lazy tricks to try to minimize TLB flushes.
675  * - The ASID changed from what cpu_tlbstate thinks it is (most likely
679  * - The TLB contains junk in slots corresponding to inactive ASIDs.
681  * - The CPU went so far out to lunch that it may have missed a TLB
692 	WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));  in initialize_tlbstate_and_flush()
702 	/* Force ASID 0 and force a TLB flush. */  in initialize_tlbstate_and_flush()
703 	write_cr3(build_cr3(mm->pgd, 0));  in initialize_tlbstate_and_flush()
709 	this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);  in initialize_tlbstate_and_flush()
718  * TLB fills that happen after we flush the TLB are ordered after we
728 	 * - mm_tlb_gen:     the latest generation.  in flush_tlb_func()
729 	 * - local_tlb_gen:  the generation that this CPU has already caught  in flush_tlb_func()
731 	 * - f->new_tlb_gen: the generation that the requester of the flush  in flush_tlb_func()
738 	bool local = smp_processor_id() == f->initiating_cpu;  in flush_tlb_func()
750 		if (f->mm && f->mm != loaded_mm)  in flush_tlb_func()
758 		   loaded_mm->context.ctx_id);  in flush_tlb_func()
763 		 * paging-structure cache to avoid speculatively reading  in flush_tlb_func()
764 		 * garbage into our TLB.  Since switching to init_mm is barely  in flush_tlb_func()
768 		 * IPIs to lazy TLB mode CPUs.  in flush_tlb_func()
774 	if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&  in flush_tlb_func()
775 		     f->new_tlb_gen <= local_tlb_gen)) {  in flush_tlb_func()
777 		 * The TLB is already up to date in respect to f->new_tlb_gen.  in flush_tlb_func()
789 	mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);  in flush_tlb_func()
794 		 * happen if two concurrent flushes happen -- the first flush to  in flush_tlb_func()
802 	WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);  in flush_tlb_func()
805 	 * If we get to this point, we know that our TLB is out of date.  in flush_tlb_func()
807 	 * possible that f->new_tlb_gen <= local_tlb_gen), but we're  in flush_tlb_func()
816 	 * 1. f->new_tlb_gen == local_tlb_gen + 1.  We have an invariant that  in flush_tlb_func()
819 	 *    f->new_tlb_gen == 3, then we know that the flush needed to bring  in flush_tlb_func()
830 	 *    3, we'd be break the invariant: we'd update local_tlb_gen above  in flush_tlb_func()
833 	 * 2. f->new_tlb_gen == mm_tlb_gen.  This is purely an optimization.  in flush_tlb_func()
834 	 *    Partial TLB flushes are not all that much cheaper than full TLB  in flush_tlb_func()
836 	 *    to do a partial flush if that won't bring our TLB fully up to  in flush_tlb_func()
841 	if (f->end != TLB_FLUSH_ALL &&  in flush_tlb_func()
842 	    f->new_tlb_gen == local_tlb_gen + 1 &&  in flush_tlb_func()
843 	    f->new_tlb_gen == mm_tlb_gen) {  in flush_tlb_func()
845 		unsigned long addr = f->start;  in flush_tlb_func()
848 		VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);  in flush_tlb_func()
851 		VM_WARN_ON(f->mm == NULL);  in flush_tlb_func()
853 		nr_invalidate = (f->end - f->start) >> f->stride_shift;  in flush_tlb_func()
855 		while (addr < f->end) {  in flush_tlb_func()
857 			addr += 1UL << f->stride_shift;  in flush_tlb_func()
876 				(f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :  in flush_tlb_func()
894 	 * cases in which a remote TLB flush will be traced, but eventually  in native_flush_tlb_multi()
898 	if (info->end == TLB_FLUSH_ALL)  in native_flush_tlb_multi()
902 				(info->end - info->start) >> PAGE_SHIFT);  in native_flush_tlb_multi()
906 	 * CPUs in lazy TLB mode. They will flush the CPU themselves  in native_flush_tlb_multi()
910 	 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping  in native_flush_tlb_multi()
914 	if (info->freed_tables)  in native_flush_tlb_multi()
928  * See Documentation/x86/tlb.rst for details.  We choose 33
954 	 * Ensure that the following code is non-reentrant and flush_tlb_info  in get_flush_tlb_info()
955 	 * is not overwritten. This means no TLB flushing is initiated by  in get_flush_tlb_info()
956 	 * interrupt handlers and machine-check exception handlers.  in get_flush_tlb_info()
961 	info->start		= start;  in get_flush_tlb_info()
962 	info->end		= end;  in get_flush_tlb_info()
963 	info->mm		= mm;  in get_flush_tlb_info()
964 	info->stride_shift	= stride_shift;  in get_flush_tlb_info()
965 	info->freed_tables	= freed_tables;  in get_flush_tlb_info()
966 	info->new_tlb_gen	= new_tlb_gen;  in get_flush_tlb_info()
967 	info->initiating_cpu	= smp_processor_id();  in get_flush_tlb_info()
993 	    ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {  in flush_tlb_mm_range()
1006 	 * a local TLB flush is needed. Optimize this use-case by calling  in flush_tlb_mm_range()
1041 	for (addr = f->start; addr < f->end; addr += PAGE_SIZE)  in do_kernel_range_flush()
1049 	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {  in flush_tlb_kernel_range()
1074 	unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,  in __get_current_cr3_fast()
1098 	 * If PTI is on, then the kernel is mapped with non-global PTEs, and  in flush_tlb_one_kernel()
1163 	 * Read-modify-write to CR4 - protect it from preemption and  in native_flush_tlb_global()
1188 	/* If current->mm == NULL then the read_cr3() "borrows" an mm */  in native_flush_tlb_local()
1212 		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.  in __flush_tlb_all()
1229 	 * a local TLB flush is needed. Optimize this use-case by calling  in arch_tlbbatch_flush()
1232 	if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {  in arch_tlbbatch_flush()
1233 		flush_tlb_multi(&batch->cpumask, info);  in arch_tlbbatch_flush()
1234 	} else if (cpumask_test_cpu(cpu, &batch->cpumask)) {  in arch_tlbbatch_flush()
1241 	cpumask_clear(&batch->cpumask);  in arch_tlbbatch_flush()
1257 	struct mm_struct *current_mm = current->mm;  in nmi_uaccess_okay()
1263 	 * current_mm->pgd == __va(read_cr3_pa()).  This may be slow, though,  in nmi_uaccess_okay()
1269 	 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.  in nmi_uaccess_okay()
1274 	VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));  in nmi_uaccess_okay()
1296 	len = min(count, sizeof(buf) - 1);  in tlbflush_write_file()
1298 		return -EFAULT;  in tlbflush_write_file()
1302 		return -EINVAL;  in tlbflush_write_file()
1305 		return -EINVAL;  in tlbflush_write_file()