Lines Matching +full:reserved +full:- +full:ipi +full:- +full:vectors
1 // SPDX-License-Identifier: GPL-2.0-only
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
69 /* step-by-step approximation to mitigate fluctuation */
81 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
92 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
104 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
114 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi()
116 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
117 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
147 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
153 (kvm_mwait_in_guest(vcpu->kvm) || kvm_hlt_in_guest(vcpu->kvm)); in kvm_can_post_timer_interrupt()
159 && !(kvm_mwait_in_guest(vcpu->kvm) || in kvm_can_use_hv_timer()
166 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; in kvm_use_posted_timer_interrupt()
171 switch (map->mode) { in kvm_apic_map_get_logical_dest()
174 u32 max_apic_id = map->max_apic_id; in kvm_apic_map_get_logical_dest()
177 u8 cluster_size = min(max_apic_id - offset + 1, 16U); in kvm_apic_map_get_logical_dest()
179 offset = array_index_nospec(offset, map->max_apic_id + 1); in kvm_apic_map_get_logical_dest()
180 *cluster = &map->phys_map[offset]; in kvm_apic_map_get_logical_dest()
181 *mask = dest_id & (0xffff >> (16 - cluster_size)); in kvm_apic_map_get_logical_dest()
189 *cluster = map->xapic_flat_map; in kvm_apic_map_get_logical_dest()
193 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; in kvm_apic_map_get_logical_dest()
210 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
212 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
228 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */ in kvm_recalculate_apic_map()
229 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN) in kvm_recalculate_apic_map()
233 "Dirty APIC map without an in-kernel local APIC"); in kvm_recalculate_apic_map()
235 mutex_lock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
237 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map in kvm_recalculate_apic_map()
240 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
243 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
249 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
258 new->max_apic_id = max_id; in kvm_recalculate_apic_map()
261 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_apic_map()
276 x2apic_id <= new->max_apic_id) in kvm_recalculate_apic_map()
277 new->phys_map[x2apic_id] = apic; in kvm_recalculate_apic_map()
279 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, in kvm_recalculate_apic_map()
282 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_apic_map()
283 new->phys_map[xapic_id] = apic; in kvm_recalculate_apic_map()
291 new->mode |= KVM_APIC_MODE_X2APIC; in kvm_recalculate_apic_map()
295 new->mode |= KVM_APIC_MODE_XAPIC_FLAT; in kvm_recalculate_apic_map()
297 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; in kvm_recalculate_apic_map()
304 cluster[ffs(mask) - 1] = apic; in kvm_recalculate_apic_map()
307 old = rcu_dereference_protected(kvm->arch.apic_map, in kvm_recalculate_apic_map()
308 lockdep_is_held(&kvm->arch.apic_map_lock)); in kvm_recalculate_apic_map()
309 rcu_assign_pointer(kvm->arch.apic_map, new); in kvm_recalculate_apic_map()
311 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
314 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
316 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
319 call_rcu(&old->rcu, kvm_apic_map_free); in kvm_recalculate_apic_map()
330 if (enabled != apic->sw_enabled) { in apic_set_spiv()
331 apic->sw_enabled = enabled; in apic_set_spiv()
337 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
342 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
348 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
354 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
360 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
372 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
376 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
386 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
391 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
396 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
406 return apic->nr_lvt_entries > lvt_index; in kvm_lapic_lvt_supported()
411 return KVM_APIC_MAX_NR_LVT_ENTRIES - !(vcpu->arch.mcg_cap & MCG_CMCI_P); in kvm_apic_calc_nr_lvt_entries()
416 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version()
422 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16); in kvm_apic_set_version()
425 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) in kvm_apic_set_version()
427 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC in kvm_apic_set_version()
428 * version first and level-triggered interrupts never get EOIed in in kvm_apic_set_version()
432 !ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_version()
440 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_after_set_mcg_cap()
443 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries) in kvm_apic_after_set_mcg_cap()
447 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++) in kvm_apic_after_set_mcg_cap()
450 apic->nr_lvt_entries = nr_lvt_entries; in kvm_apic_after_set_mcg_cap()
471 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; in find_highest_vector()
472 vec >= 0; vec -= APIC_VECTORS_PER_REG) { in find_highest_vector()
478 return -1; in find_highest_vector()
501 max_updated_irr = -1; in __kvm_apic_update_irr()
502 *max_irr = -1; in __kvm_apic_update_irr()
520 return ((max_updated_irr != -1) && in __kvm_apic_update_irr()
527 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr()
529 return __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
535 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
546 if (!apic->irr_pending) in apic_find_highest_irr()
547 return -1; in apic_find_highest_irr()
550 ASSERT(result == -1 || result >= 16); in apic_find_highest_irr()
557 if (unlikely(apic->apicv_active)) { in apic_clear_irr()
559 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
560 static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu, in apic_clear_irr()
563 apic->irr_pending = false; in apic_clear_irr()
564 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
565 if (apic_search_irr(apic) != -1) in apic_clear_irr()
566 apic->irr_pending = true; in apic_clear_irr()
572 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
578 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
586 if (unlikely(apic->apicv_active)) in apic_set_isr()
589 ++apic->isr_count; in apic_set_isr()
590 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
596 apic->highest_isr_cache = vec; in apic_set_isr()
606 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
608 if (!apic->isr_count) in apic_find_highest_isr()
609 return -1; in apic_find_highest_isr()
610 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
611 return apic->highest_isr_cache; in apic_find_highest_isr()
613 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
614 ASSERT(result == -1 || result >= 16); in apic_find_highest_isr()
621 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
626 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
631 if (unlikely(apic->apicv_active)) in apic_clear_isr()
634 --apic->isr_count; in apic_clear_isr()
635 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
636 apic->highest_isr_cache = -1; in apic_clear_isr()
647 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
658 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq()
660 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
661 irq->level, irq->trig_mode, dest_map); in kvm_apic_set_irq()
670 if (min > map->max_apic_id) in __pv_send_ipi()
674 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { in __pv_send_ipi()
675 if (map->phys_map[min + i]) { in __pv_send_ipi()
676 vcpu = map->phys_map[min + i]->vcpu; in __pv_send_ipi()
694 return -KVM_EINVAL; in kvm_pv_send_ipi()
702 map = rcu_dereference(kvm->arch.apic_map); in kvm_pv_send_ipi()
704 count = -EOPNOTSUPP; in kvm_pv_send_ipi()
718 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, in pv_eoi_put_user()
725 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, in pv_eoi_get_user()
731 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; in pv_eoi_enabled()
739 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_set_pending()
759 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_test_and_clr_pending()
768 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); in apic_has_interrupt_for_ppr()
771 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) in apic_has_interrupt_for_ppr()
772 return -1; in apic_has_interrupt_for_ppr()
784 isrv = (isr != -1) ? isr : 0; in __apic_update_ppr()
803 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
804 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
809 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
873 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
877 * - in-kernel IOAPIC messages have to be delivered directly to
880 * rewrites the destination of non-IPI messages from APIC_BROADCAST
884 * important when userspace wants to use x2APIC-format MSIs, because
885 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
890 bool ipi = source != NULL; in kvm_apic_mda() local
892 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && in kvm_apic_mda()
893 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) in kvm_apic_mda()
902 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
928 int i, idx = -1; in kvm_vector_to_index()
942 if (!kvm->arch.disabled_lapic_found) { in kvm_apic_disabled_lapic_found()
943 kvm->arch.disabled_lapic_found = true; in kvm_apic_disabled_lapic_found()
952 if (kvm->arch.x2apic_broadcast_quirk_disabled) { in kvm_apic_is_broadcast_dest()
953 if ((irq->dest_id == APIC_BROADCAST && in kvm_apic_is_broadcast_dest()
954 map->mode != KVM_APIC_MODE_X2APIC)) in kvm_apic_is_broadcast_dest()
956 if (irq->dest_id == X2APIC_BROADCAST) in kvm_apic_is_broadcast_dest()
960 if (irq->dest_id == (x2apic_ipi ? in kvm_apic_is_broadcast_dest()
982 if (irq->shorthand == APIC_DEST_SELF && src) { in kvm_apic_map_get_dest_lapic()
986 } else if (irq->shorthand) in kvm_apic_map_get_dest_lapic()
992 if (irq->dest_mode == APIC_DEST_PHYSICAL) { in kvm_apic_map_get_dest_lapic()
993 if (irq->dest_id > map->max_apic_id) { in kvm_apic_map_get_dest_lapic()
996 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1); in kvm_apic_map_get_dest_lapic()
997 *dst = &map->phys_map[dest_id]; in kvm_apic_map_get_dest_lapic()
1004 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, in kvm_apic_map_get_dest_lapic()
1012 lowest = -1; in kvm_apic_map_get_dest_lapic()
1018 else if (kvm_apic_compare_prio((*dst)[i]->vcpu, in kvm_apic_map_get_dest_lapic()
1019 (*dst)[lowest]->vcpu) < 0) in kvm_apic_map_get_dest_lapic()
1026 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), in kvm_apic_map_get_dest_lapic()
1050 *r = -1; in kvm_irq_delivery_to_apic_fast()
1052 if (irq->shorthand == APIC_DEST_SELF) { in kvm_irq_delivery_to_apic_fast()
1057 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1062 map = rcu_dereference(kvm->arch.apic_map); in kvm_irq_delivery_to_apic_fast()
1070 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1081 * - For single-destination interrupts, handle it in posted mode
1082 * - Else if vector hashing is enabled and it is a lowest-priority
1085 * 1. For lowest-priority interrupts, store all the possible
1088 * the right destination vCPU in the array for the lowest-priority
1090 * - Otherwise, use remapped mode to inject the interrupt.
1100 if (irq->shorthand) in kvm_intr_is_single_vcpu_fast()
1104 map = rcu_dereference(kvm->arch.apic_map); in kvm_intr_is_single_vcpu_fast()
1111 *dest_vcpu = dst[i]->vcpu; in kvm_intr_is_single_vcpu_fast()
1129 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1131 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, in __apic_accept_irq()
1135 vcpu->arch.apic_arb_prio++; in __apic_accept_irq()
1148 __set_bit(vcpu->vcpu_id, dest_map->map); in __apic_accept_irq()
1149 dest_map->vectors[vcpu->vcpu_id] = vector; in __apic_accept_irq()
1152 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1155 apic->regs + APIC_TMR); in __apic_accept_irq()
1158 apic->regs + APIC_TMR); in __apic_accept_irq()
1167 vcpu->arch.pv.pv_unhalted = 1; in __apic_accept_irq()
1188 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1196 apic->sipi_vector = vector; in __apic_accept_irq()
1199 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1238 map = rcu_dereference(kvm->arch.apic_map); in kvm_bitmap_or_dest_vcpus()
1246 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx; in kvm_bitmap_or_dest_vcpus()
1254 irq->shorthand, in kvm_bitmap_or_dest_vcpus()
1255 irq->dest_id, in kvm_bitmap_or_dest_vcpus()
1256 irq->dest_mode)) in kvm_bitmap_or_dest_vcpus()
1266 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; in kvm_apic_compare_prio()
1271 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1283 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1284 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1285 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1289 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1294 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1307 if (vector == -1) in apic_set_eoi()
1313 if (to_hv_vcpu(apic->vcpu) && in apic_set_eoi()
1314 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1315 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1318 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1323 * this interface assumes a trap-like exit, which has already finished
1328 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated()
1333 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1358 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1372 apic->lapic_timer.period == 0) in apic_get_tmcct()
1376 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1380 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1382 (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1389 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1390 struct kvm_run *run = vcpu->run; in __report_tpr_access()
1393 run->tpr_access.rip = kvm_rip_read(vcpu); in __report_tpr_access()
1394 run->tpr_access.is_write = write; in __report_tpr_access()
1399 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1442 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1449 /* this bitmask has a bit cleared for each reserved register */ in kvm_lapic_reg_read()
1478 * in x2APIC mode as it's an 8-byte register in x2APIC and needs to be in kvm_lapic_reg_read()
1513 return addr >= apic->base_address && in apic_mmio_in_range()
1514 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1521 u32 offset = address - apic->base_address; in apic_mmio_read()
1524 return -EOPNOTSUPP; in apic_mmio_read()
1527 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_read()
1529 return -EOPNOTSUPP; in apic_mmio_read()
1547 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1557 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1560 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1564 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1565 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1566 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1575 hrtimer_cancel(&apic->lapic_timer.timer); in cancel_apic_timer()
1577 if (apic->lapic_timer.hv_timer_in_use) in cancel_apic_timer()
1580 atomic_set(&apic->lapic_timer.pending, 0); in cancel_apic_timer()
1586 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1588 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1593 apic->lapic_timer.period = 0; in apic_update_lvtt()
1594 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1596 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1603 * during a higher-priority task.
1608 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected()
1613 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1615 if (apic->apicv_active) in lapic_timer_int_injected()
1616 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1626 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1634 if (vcpu->arch.tsc_scaling_ratio == kvm_caps.default_tsc_scaling_ratio) { in __wait_lapic_expire()
1639 do_div(delay_ns, vcpu->arch.virtual_tsc_khz); in __wait_lapic_expire()
1647 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance()
1648 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1658 ns = -advance_expire_delta * 1000000ULL; in adjust_lapic_timer_advance()
1659 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1660 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; in adjust_lapic_timer_advance()
1664 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1670 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1675 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire()
1678 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1679 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1681 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1684 adjust_lapic_timer_advance(vcpu, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1695 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc); in __kvm_wait_lapic_expire()
1701 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1702 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1710 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1714 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1716 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1717 ktimer->target_expiration = 0; in kvm_apic_inject_pending_timer_irqs()
1723 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1724 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1726 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1729 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1730 ktimer->expired_tscdeadline = ktimer->tscdeadline; in apic_timer_expired()
1732 if (!from_timer_fn && apic->apicv_active) { in apic_timer_expired()
1738 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1746 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1747 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1753 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1761 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1762 u64 guest_tsc, tscdeadline = ktimer->tscdeadline; in start_sw_tscdeadline()
1765 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1766 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; in start_sw_tscdeadline()
1778 ns = (tscdeadline - guest_tsc) * 1000000ULL; in start_sw_tscdeadline()
1782 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1784 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); in start_sw_tscdeadline()
1785 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD); in start_sw_tscdeadline()
1794 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1802 apic->lapic_timer.period = in update_target_expiration()
1807 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1813 apic->divide_count, old_divisor); in update_target_expiration()
1815 apic->lapic_timer.tscdeadline += in update_target_expiration()
1816 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1817 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1818 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1828 apic->lapic_timer.period = in set_target_expiration()
1831 if (!apic->lapic_timer.period) { in set_target_expiration()
1832 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
1837 deadline = apic->lapic_timer.period; in set_target_expiration()
1844 deadline = apic->lapic_timer.period; in set_target_expiration()
1845 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
1850 apic->vcpu->vcpu_id, in set_target_expiration()
1853 deadline, apic->lapic_timer.period); in set_target_expiration()
1855 deadline = apic->lapic_timer.period; in set_target_expiration()
1860 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
1861 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
1862 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
1880 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
1881 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
1882 apic->lapic_timer.period); in advance_periodic_target_expiration()
1883 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
1884 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
1885 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
1890 if (!apic->lapic_timer.period) in start_sw_period()
1894 apic->lapic_timer.target_expiration)) { in start_sw_period()
1903 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
1904 apic->lapic_timer.target_expiration, in start_sw_period()
1913 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
1920 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
1921 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); in cancel_hv_timer()
1922 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
1927 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
1928 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
1935 if (!ktimer->tscdeadline) in start_hv_timer()
1938 if (static_call(kvm_x86_set_hv_timer)(vcpu, ktimer->tscdeadline, &expired)) in start_hv_timer()
1941 ktimer->hv_timer_in_use = true; in start_hv_timer()
1942 hrtimer_cancel(&ktimer->timer); in start_hv_timer()
1947 * VM-Exit to recompute the periodic timer's target expiration. in start_hv_timer()
1954 if (atomic_read(&ktimer->pending)) { in start_hv_timer()
1962 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use); in start_hv_timer()
1969 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
1972 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
1974 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
1981 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
1988 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
1999 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer()
2003 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
2009 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
2020 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
2025 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer()
2029 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
2036 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer()
2038 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
2044 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
2062 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
2063 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
2065 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2067 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2073 struct kvm *kvm = apic->vcpu->kvm; in kvm_lapic_xapic_id_updated()
2078 if (kvm_xapic_id(apic) == apic->vcpu->vcpu_id) in kvm_lapic_xapic_id_updated()
2081 kvm_set_apicv_inhibit(apic->vcpu->kvm, APICV_INHIBIT_REASON_APIC_ID_MODIFIED); in kvm_lapic_xapic_id_updated()
2089 return -1; in get_lvt_index()
2091 (reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES); in get_lvt_index()
2141 for (i = 0; i < apic->nr_lvt_entries; i++) { in kvm_lapic_reg_write()
2146 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2189 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2204 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2208 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2209 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2210 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2237 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2246 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2250 return -EOPNOTSUPP; in apic_mmio_write()
2253 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_write()
2255 return -EOPNOTSUPP; in apic_mmio_write()
2261 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2277 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2284 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_write_nodecode()
2288 if (KVM_BUG_ON(kvm_lapic_msr_read(apic, offset, &val), vcpu->kvm)) in kvm_apic_write_nodecode()
2295 * ICR is a single 64-bit register when x2APIC is enabled. For legacy in kvm_apic_write_nodecode()
2311 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic()
2313 if (!vcpu->arch.apic) in kvm_free_lapic()
2316 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2318 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()
2321 if (!apic->sw_enabled) in kvm_free_lapic()
2324 if (apic->regs) in kvm_free_lapic()
2325 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2331 *----------------------------------------------------------------------
2333 *----------------------------------------------------------------------
2337 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr()
2342 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2347 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr()
2352 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2353 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2359 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2366 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2373 u64 old_value = vcpu->arch.apic_base; in kvm_lapic_set_base()
2374 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base()
2376 vcpu->arch.apic_base = value; in kvm_lapic_set_base()
2387 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2393 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2398 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2405 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2409 apic->base_address != APIC_DEFAULT_PHYS_BASE) { in kvm_lapic_set_base()
2410 kvm_set_apicv_inhibit(apic->vcpu->kvm, in kvm_lapic_set_base()
2417 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv()
2419 if (apic->apicv_active) { in kvm_apic_update_apicv()
2421 apic->irr_pending = true; in kvm_apic_update_apicv()
2422 apic->isr_count = 1; in kvm_apic_update_apicv()
2430 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2437 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset()
2452 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2456 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2457 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2459 for (i = 0; i < apic->nr_lvt_entries; i++) in kvm_lapic_reset()
2463 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) in kvm_lapic_reset()
2488 apic->highest_isr_cache = -1; in kvm_lapic_reset()
2490 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2492 vcpu->arch.pv_eoi.msr_val = 0; in kvm_lapic_reset()
2494 if (apic->apicv_active) { in kvm_lapic_reset()
2496 static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, -1); in kvm_lapic_reset()
2497 static_call_cond(kvm_x86_hwapic_isr_update)(-1); in kvm_lapic_reset()
2500 vcpu->arch.apic_arb_prio = 0; in kvm_lapic_reset()
2501 vcpu->arch.apic_attention = 0; in kvm_lapic_reset()
2503 kvm_recalculate_apic_map(vcpu->kvm); in kvm_lapic_reset()
2507 *----------------------------------------------------------------------
2509 *----------------------------------------------------------------------
2519 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer()
2522 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2544 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver()
2564 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); in apic_timer_fn()
2580 vcpu->arch.apic = apic; in kvm_create_lapic()
2582 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2583 if (!apic->regs) { in kvm_create_lapic()
2585 vcpu->vcpu_id); in kvm_create_lapic()
2588 apic->vcpu = vcpu; in kvm_create_lapic()
2590 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu); in kvm_create_lapic()
2592 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2594 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2595 if (timer_advance_ns == -1) { in kvm_create_lapic()
2596 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2599 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2607 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()
2609 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2614 vcpu->arch.apic = NULL; in kvm_create_lapic()
2616 return -ENOMEM; in kvm_create_lapic()
2621 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt()
2625 return -1; in kvm_apic_has_interrupt()
2634 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2636 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2646 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs()
2648 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2650 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2657 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt()
2660 if (vector == -1) in kvm_get_apic_interrupt()
2661 return -1; in kvm_get_apic_interrupt()
2671 if (to_hv_vcpu(vcpu) && test_bit(vector, to_hv_synic(vcpu)->auto_eoi_bitmap)) { in kvm_get_apic_interrupt()
2673 * For auto-EOI interrupts, there might be another pending in kvm_get_apic_interrupt()
2681 * be a higher-priority pending interrupt---except if there was in kvm_get_apic_interrupt()
2695 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2696 u32 *id = (u32 *)(s->regs + APIC_ID); in kvm_apic_state_fixup()
2697 u32 *ldr = (u32 *)(s->regs + APIC_LDR); in kvm_apic_state_fixup()
2700 if (vcpu->kvm->arch.x2apic_format) { in kvm_apic_state_fixup()
2701 if (*id != vcpu->vcpu_id) in kvm_apic_state_fixup()
2702 return -EINVAL; in kvm_apic_state_fixup()
2712 * ICR is internally a single 64-bit register, but needs to be in kvm_apic_state_fixup()
2718 icr = __kvm_lapic_get_reg(s->regs, APIC_ICR) | in kvm_apic_state_fixup()
2719 (u64)__kvm_lapic_get_reg(s->regs, APIC_ICR2) << 32; in kvm_apic_state_fixup()
2720 __kvm_lapic_set_reg64(s->regs, APIC_ICR, icr); in kvm_apic_state_fixup()
2722 icr = __kvm_lapic_get_reg64(s->regs, APIC_ICR); in kvm_apic_state_fixup()
2723 __kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32); in kvm_apic_state_fixup()
2726 kvm_lapic_xapic_id_updated(vcpu->arch.apic); in kvm_apic_state_fixup()
2734 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
2740 __kvm_lapic_set_reg(s->regs, APIC_TMCCT, in kvm_apic_get_state()
2741 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
2748 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state()
2751 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); in kvm_apic_set_state()
2753 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
2757 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
2760 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
2762 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
2763 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
2768 apic->lapic_timer.expired_tscdeadline = 0; in kvm_apic_set_state()
2775 apic->highest_isr_cache = -1; in kvm_apic_set_state()
2776 if (apic->apicv_active) { in kvm_apic_set_state()
2782 if (ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_state()
2785 vcpu->arch.apic_arb_prio = 0; in kvm_apic_set_state()
2798 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
2804 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2819 * -> host disabled PV EOI. in apic_sync_pv_eoi_from_guest()
2821 * -> host enabled PV EOI, guest did not execute EOI yet. in apic_sync_pv_eoi_from_guest()
2823 * -> host enabled PV EOI, guest executed EOI. in apic_sync_pv_eoi_from_guest()
2837 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
2838 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
2840 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
2843 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
2847 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
2851 * apic_sync_pv_eoi_to_guest - called before vmentry
2861 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
2863 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
2865 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
2873 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
2880 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic()
2884 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_to_vapic()
2896 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
2903 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, in kvm_lapic_set_vapic_addr()
2904 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
2906 return -EINVAL; in kvm_lapic_set_vapic_addr()
2907 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
2909 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
2912 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
2946 * ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and in kvm_lapic_msr_write()
2948 * through 32-bit reads/writes. in kvm_lapic_msr_write()
2958 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write()
2959 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_write()
2969 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read()
2970 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_read()
2986 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_write()
2994 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_read()
3000 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; in kvm_lapic_set_pv_eoi()
3008 if (addr == ghc->gpa && len <= ghc->len) in kvm_lapic_set_pv_eoi()
3009 new_len = ghc->len; in kvm_lapic_set_pv_eoi()
3013 ret = kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); in kvm_lapic_set_pv_eoi()
3018 vcpu->arch.pv_eoi.msr_val = data; in kvm_lapic_set_pv_eoi()
3025 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events()
3035 return r == -EBUSY ? 0 : r; in kvm_apic_accept_events()
3037 * Continue processing INIT/SIPI even if a nested VM-Exit in kvm_apic_accept_events()
3046 * wait-for-SIPI (WFS). in kvm_apic_accept_events()
3049 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); in kvm_apic_accept_events()
3050 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
3054 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { in kvm_apic_accept_events()
3056 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
3057 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()
3059 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; in kvm_apic_accept_events()
3061 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { in kvm_apic_accept_events()
3062 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { in kvm_apic_accept_events()
3065 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()
3067 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()