Lines Matching +full:ecx +full:- +full:2000
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
34 #include <asm/intel-family.h>
58 if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) in find_matching_signature()
68 for (i = 0; i < ext_hdr->count; i++) { in find_matching_signature()
69 if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) in find_matching_signature()
83 if (mc_hdr->rev <= new_rev) in has_newer_microcode()
97 p->data = kmemdup(data, size, GFP_KERNEL); in memdup_patch()
98 if (!p->data) { in memdup_patch()
116 mc_saved_hdr = (struct microcode_header_intel *)iter->data; in save_microcode_patch()
117 sig = mc_saved_hdr->sig; in save_microcode_patch()
118 pf = mc_saved_hdr->pf; in save_microcode_patch()
123 if (mc_hdr->rev <= mc_saved_hdr->rev) in save_microcode_patch()
130 list_replace(&iter->plist, &p->plist); in save_microcode_patch()
131 kfree(iter->data); in save_microcode_patch()
146 list_add_tail(&p->plist, µcode_cache); in save_microcode_patch()
152 if (!find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) in save_microcode_patch()
156 * Save for early loading. On 32-bit, that needs to be a physical in save_microcode_patch()
161 intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); in save_microcode_patch()
163 intel_ucode_patch = p->data; in save_microcode_patch()
180 return -EINVAL; in microcode_sanity_check()
183 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) { in microcode_sanity_check()
186 return -EINVAL; in microcode_sanity_check()
189 ext_table_size = total_size - (MC_HEADER_SIZE + data_size); in microcode_sanity_check()
195 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { in microcode_sanity_check()
198 return -EINVAL; in microcode_sanity_check()
205 return -EFAULT; in microcode_sanity_check()
208 ext_sigcount = ext_header->count; in microcode_sanity_check()
217 while (i--) in microcode_sanity_check()
223 return -EINVAL; in microcode_sanity_check()
234 while (i--) in microcode_sanity_check()
240 return -EINVAL; in microcode_sanity_check()
253 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - in microcode_sanity_check()
254 (ext_sig->sig + ext_sig->pf + ext_sig->cksum); in microcode_sanity_check()
258 return -EINVAL; in microcode_sanity_check()
287 size -= mc_size; in scan_microcode()
289 if (!find_matching_signature(data, uci->cpu_sig.sig, in scan_microcode()
290 uci->cpu_sig.pf)) { in scan_microcode()
303 uci->cpu_sig.sig, in scan_microcode()
304 uci->cpu_sig.pf, in scan_microcode()
305 uci->cpu_sig.rev)) in scan_microcode()
309 struct microcode_header_intel *phdr = &patch->hdr; in scan_microcode()
312 phdr->sig, in scan_microcode()
313 phdr->pf, in scan_microcode()
314 phdr->rev)) in scan_microcode()
357 mc_saved_header = (struct microcode_header_intel *)p->data; in show_saved_mc()
359 sig = mc_saved_header->sig; in show_saved_mc()
360 pf = mc_saved_header->pf; in show_saved_mc()
361 rev = mc_saved_header->rev; in show_saved_mc()
362 date = mc_saved_header->date; in show_saved_mc()
367 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", in show_saved_mc()
378 ext_sigcount = ext_header->count; in show_saved_mc()
382 sig = ext_sig->sig; in show_saved_mc()
383 pf = ext_sig->pf; in show_saved_mc()
396 * hot-added or resumes.
413 unsigned int eax = 1, ebx, ecx = 0, edx; in load_builtin_intel_microcode() local
420 native_cpuid(&eax, &ebx, &ecx, &edx); in load_builtin_intel_microcode()
422 sprintf(name, "intel-ucode/%02x-%02x-%02x", in load_builtin_intel_microcode()
426 cp->size = fw.size; in load_builtin_intel_microcode()
427 cp->data = (void *)fw.data; in load_builtin_intel_microcode()
440 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", in print_ucode_info()
441 uci->cpu_sig.rev, in print_ucode_info()
476 mc = uci->mc; in print_ucode()
484 *current_mc_date_p = mc->hdr.date; in print_ucode()
492 mc = uci->mc; in print_ucode()
496 print_ucode_info(uci, mc->hdr.date); in print_ucode()
505 mc = uci->mc; in apply_microcode_early()
510 * Save us the MSR write below - which is a particular expensive in apply_microcode_early()
511 * operation - when the other hyperthread has updated the microcode in apply_microcode_early()
515 if (rev >= mc->hdr.rev) { in apply_microcode_early()
516 uci->cpu_sig.rev = rev; in apply_microcode_early()
527 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in apply_microcode_early()
530 if (rev != mc->hdr.rev) in apply_microcode_early()
531 return -1; in apply_microcode_early()
533 uci->cpu_sig.rev = rev; in apply_microcode_early()
538 print_ucode_info(uci, mc->hdr.date); in apply_microcode_early()
588 /* try built-in microcode first */ in __load_ucode_intel()
636 /* Mixed-silicon system? Try to refetch the proper patch: */ in load_ucode_intel_ap()
650 phdr = (struct microcode_header_intel *)iter->data; in find_patch()
652 if (phdr->rev <= uci->cpu_sig.rev) in find_patch()
656 uci->cpu_sig.sig, in find_patch()
657 uci->cpu_sig.pf)) in find_patch()
660 return iter->data; in find_patch()
689 csig->sig = cpuid_eax(0x00000001); in collect_cpu_info()
691 if ((c->x86_model >= 5) || (c->x86 > 6)) { in collect_cpu_info()
694 csig->pf = 1 << ((val[1] >> 18) & 7); in collect_cpu_info()
697 csig->rev = c->microcode; in collect_cpu_info()
700 if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { in collect_cpu_info()
702 csig->sig, csig->pf, csig->rev); in collect_cpu_info()
713 bool bsp = c->cpu_index == boot_cpu_data.cpu_index; in apply_microcode_intel()
726 mc = uci->mc; in apply_microcode_intel()
732 * Save us the MSR write below - which is a particular expensive in apply_microcode_intel()
733 * operation - when the other hyperthread has updated the microcode in apply_microcode_intel()
737 if (rev >= mc->hdr.rev) { in apply_microcode_intel()
749 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in apply_microcode_intel()
753 if (rev != mc->hdr.rev) { in apply_microcode_intel()
755 cpu, mc->hdr.rev); in apply_microcode_intel()
760 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", in apply_microcode_intel()
762 mc->hdr.date & 0xffff, in apply_microcode_intel()
763 mc->hdr.date >> 24, in apply_microcode_intel()
764 (mc->hdr.date >> 16) & 0xff); in apply_microcode_intel()
771 uci->cpu_sig.rev = rev; in apply_microcode_intel()
772 c->microcode = rev; in apply_microcode_intel()
786 int new_rev = uci->cpu_sig.rev; in generic_load_microcode()
805 data_size = mc_size - sizeof(mc_header); in generic_load_microcode()
827 csig = uci->cpu_sig.sig; in generic_load_microcode()
828 cpf = uci->cpu_sig.pf; in generic_load_microcode()
849 vfree(uci->mc); in generic_load_microcode()
850 uci->mc = (struct microcode_intel *)new_mc; in generic_load_microcode()
860 cpu, new_rev, uci->cpu_sig.rev); in generic_load_microcode()
873 * Processor E7-8800/4800 v4 Product Family). in is_blacklisted()
875 if (c->x86 == 6 && in is_blacklisted()
876 c->x86_model == INTEL_FAM6_BROADWELL_X && in is_blacklisted()
877 c->x86_stepping == 0x01 && in is_blacklisted()
879 c->microcode < 0x0b000021) { in is_blacklisted()
880 …pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microc… in is_blacklisted()
881 …pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS upda… in is_blacklisted()
901 sprintf(name, "intel-ucode/%02x-%02x-%02x", in request_microcode_fw()
902 c->x86, c->x86_model, c->x86_stepping); in request_microcode_fw()
909 kvec.iov_base = (void *)firmware->data; in request_microcode_fw()
910 kvec.iov_len = firmware->size; in request_microcode_fw()
911 iov_iter_kvec(&iter, WRITE, &kvec, 1, firmware->size); in request_microcode_fw()
927 u64 llc_size = c->x86_cache_size * 1024ULL; in calc_llc_size_per_core()
929 do_div(llc_size, c->x86_max_cores); in calc_llc_size_per_core()
938 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || in init_intel_microcode()
940 pr_err("Intel CPU family 0x%x not supported\n", c->x86); in init_intel_microcode()