Lines Matching +full:4 +full:c
73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) in check_memory_type_self_snoop_errata() argument
75 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) in probe_xeon_phi_r3mwait() argument
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); in probe_xeon_phi_r3mwait()
124 if (c == &boot_cpu_data) in probe_xeon_phi_r3mwait()
165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) in bad_spectre_microcode() argument
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) in bad_spectre_microcode()
176 if (c->x86 != 6) in bad_spectre_microcode()
180 if (c->x86_model == spectre_bad_microcodes[i].model && in bad_spectre_microcode()
181 c->x86_stepping == spectre_bad_microcodes[i].stepping) in bad_spectre_microcode()
182 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
219 static void early_init_intel(struct cpuinfo_x86 *c) in early_init_intel() argument
224 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
227 c->cpuid_level = cpuid_eax(0); in early_init_intel()
228 get_cpu_cap(c); in early_init_intel()
232 if ((c->x86 == 0xf && c->x86_model >= 0x03) || in early_init_intel()
233 (c->x86 == 0x6 && c->x86_model >= 0x0e)) in early_init_intel()
234 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); in early_init_intel()
236 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
237 c->microcode = intel_get_microcode_revision(); in early_init_intel()
240 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || in early_init_intel()
241 cpu_has(c, X86_FEATURE_INTEL_STIBP) || in early_init_intel()
242 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || in early_init_intel()
243 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { in early_init_intel()
263 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && in early_init_intel()
264 c->microcode < 0x20e) { in early_init_intel()
266 clear_cpu_cap(c, X86_FEATURE_PSE); in early_init_intel()
270 set_cpu_cap(c, X86_FEATURE_SYSENTER32); in early_init_intel()
273 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
274 c->x86_cache_alignment = 128; in early_init_intel()
278 if (c->x86 == 0xF && c->x86_model == 0x3 in early_init_intel()
279 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
280 c->x86_phys_bits = 36; in early_init_intel()
283 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
284 * with P/T states and does not stop in deep C-states. in early_init_intel()
289 if (c->x86_power & (1 << 8)) { in early_init_intel()
290 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); in early_init_intel()
291 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); in early_init_intel()
295 if (c->x86 == 6) { in early_init_intel()
296 switch (c->x86_model) { in early_init_intel()
301 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); in early_init_intel()
318 if (c->x86 == 6 && c->x86_model < 15) in early_init_intel()
319 clear_cpu_cap(c, X86_FEATURE_PAT); in early_init_intel()
325 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
344 if (c->x86 == 5 && c->x86_model == 9) { in early_init_intel()
349 if (c->cpuid_level >= 0x00000001) { in early_init_intel()
359 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); in early_init_intel()
362 check_memory_type_self_snoop_errata(c); in early_init_intel()
368 if (detect_extended_topology_early(c) < 0) in early_init_intel()
369 detect_ht_early(c); in early_init_intel()
372 static void bsp_init_intel(struct cpuinfo_x86 *c) in bsp_init_intel() argument
374 resctrl_cpu_detect(c); in bsp_init_intel()
397 static void intel_smp_check(struct cpuinfo_x86 *c) in intel_smp_check() argument
400 if (!c->cpu_index) in intel_smp_check()
406 if (c->x86 == 5 && in intel_smp_check()
407 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
408 c->x86_model <= 3) { in intel_smp_check()
425 static void intel_workarounds(struct cpuinfo_x86 *c) in intel_workarounds() argument
434 clear_cpu_bug(c, X86_BUG_F00F); in intel_workarounds()
435 if (c->x86 == 5 && c->x86_model < 9) { in intel_workarounds()
438 set_cpu_bug(c, X86_BUG_F00F); in intel_workarounds()
450 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
451 clear_cpu_cap(c, X86_FEATURE_SEP); in intel_workarounds()
460 set_cpu_cap(c, X86_FEATURE_PAE); in intel_workarounds()
468 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { in intel_workarounds()
482 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
483 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
484 set_cpu_bug(c, X86_BUG_11AP); in intel_workarounds()
491 switch (c->x86) { in intel_workarounds()
492 case 4: /* 486: untested */ in intel_workarounds()
505 intel_smp_check(c); in intel_workarounds()
508 static void intel_workarounds(struct cpuinfo_x86 *c) in intel_workarounds() argument
513 static void srat_detect_node(struct cpuinfo_x86 *c) in srat_detect_node() argument
536 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
550 static void detect_tme(struct cpuinfo_x86 *c) in detect_tme() argument
611 c->x86_phys_bits -= keyid_bits; in detect_tme()
614 static void init_cpuid_fault(struct cpuinfo_x86 *c) in init_cpuid_fault() argument
620 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); in init_cpuid_fault()
624 static void init_intel_misc_features(struct cpuinfo_x86 *c) in init_intel_misc_features() argument
635 init_cpuid_fault(c); in init_intel_misc_features()
636 probe_xeon_phi_r3mwait(c); in init_intel_misc_features()
645 static void init_intel(struct cpuinfo_x86 *c) in init_intel() argument
647 early_init_intel(c); in init_intel()
649 intel_workarounds(c); in init_intel()
656 detect_extended_topology(c); in init_intel()
658 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { in init_intel()
663 detect_num_cpu_cores(c); in init_intel()
665 detect_ht(c); in init_intel()
669 init_intel_cacheinfo(c); in init_intel()
671 if (c->cpuid_level > 9) { in init_intel()
675 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); in init_intel()
678 if (cpu_has(c, X86_FEATURE_XMM2)) in init_intel()
679 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); in init_intel()
686 set_cpu_cap(c, X86_FEATURE_BTS); in init_intel()
688 set_cpu_cap(c, X86_FEATURE_PEBS); in init_intel()
691 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && in init_intel()
692 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) in init_intel()
693 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); in init_intel()
695 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && in init_intel()
696 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) in init_intel()
697 set_cpu_bug(c, X86_BUG_MONITOR); in init_intel()
700 if (c->x86 == 15) in init_intel()
701 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
702 if (c->x86 == 6) in init_intel()
703 set_cpu_cap(c, X86_FEATURE_REP_GOOD); in init_intel()
710 if (c->x86 == 6) { in init_intel()
711 unsigned int l2 = c->x86_cache_size; in init_intel()
714 switch (c->x86_model) { in init_intel()
725 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
736 strcpy(c->x86_model_id, p); in init_intel()
739 if (c->x86 == 15) in init_intel()
740 set_cpu_cap(c, X86_FEATURE_P4); in init_intel()
741 if (c->x86 == 6) in init_intel()
742 set_cpu_cap(c, X86_FEATURE_P3); in init_intel()
746 srat_detect_node(c); in init_intel()
748 init_ia32_feat_ctl(c); in init_intel()
750 if (cpu_has(c, X86_FEATURE_TME)) in init_intel()
751 detect_tme(c); in init_intel()
753 init_intel_misc_features(c); in init_intel()
758 intel_init_thermal(c); in init_intel()
762 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) in intel_size_cache() argument
770 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) in intel_size_cache()
774 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
777 if ((c->x86 == 5) && (c->x86_model == 9)) in intel_size_cache()
805 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
806 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
807 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
808 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
809 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
810 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
811 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
812 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
813 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
814 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
815 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
816 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
817 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
818 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
819 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
820 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
821 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
822 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
823 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
824 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
825 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
826 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
828 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
829 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
830 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
831 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
832 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
833 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
834 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
835 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
836 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
837 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
838 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
839 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
840 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
931 static void intel_detect_tlb(struct cpuinfo_x86 *c) in intel_detect_tlb() argument
934 unsigned int regs[4]; in intel_detect_tlb()
937 if (c->cpuid_level < 2) in intel_detect_tlb()
962 { .family = 4, .model_names =
968 [4] = "486 SL",
971 [8] = "486 DX/4",
972 [9] = "486 DX/4-WB"
981 [4] = "Pentium MMX",
992 [4] = "Pentium II (Deschutes)",
1003 [0] = "Pentium 4 (Unknown)",
1004 [1] = "Pentium 4 (Willamette)",
1005 [2] = "Pentium 4 (Northwood)",
1006 [4] = "Pentium 4 (Foster)",
1007 [5] = "Pentium 4 (Foster)",
1297 static void __init split_lock_setup(struct cpuinfo_x86 *c) in split_lock_setup() argument
1313 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) in split_lock_setup()
1363 void __init sld_setup(struct cpuinfo_x86 *c) in sld_setup() argument
1365 split_lock_setup(c); in sld_setup()