Lines Matching +full:4 +full:k
407 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
450 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
482 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
492 case 4: /* 486: untested */ in intel_workarounds()
536 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
774 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
775 * 16K cache with a 16 byte cache line and 256 lines per tag in intel_size_cache()
805 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
806 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
807 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
808 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
809 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
810 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
811 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
812 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
813 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
814 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
815 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
816 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
817 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
818 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
819 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
820 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
821 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
822 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
823 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
824 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
825 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
826 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
828 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
829 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
830 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
831 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
832 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
833 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
834 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
835 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
836 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
837 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
838 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
839 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
840 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
846 unsigned char k; in intel_tlb_lookup() local
851 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
852 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
855 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
858 switch (intel_tlb_table[k].tlb_type) { in intel_tlb_lookup()
860 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
861 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
862 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
863 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
866 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
867 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
868 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
869 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
870 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
871 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
872 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
873 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
874 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
875 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
876 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
877 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
880 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
881 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
882 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
883 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
884 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
885 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
888 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
889 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
892 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
893 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
896 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
897 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
898 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
899 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
903 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
904 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
908 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
909 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
913 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
914 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
915 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
916 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
919 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
920 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
921 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
922 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
925 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
926 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
934 unsigned int regs[4]; in intel_detect_tlb()
962 { .family = 4, .model_names =
968 [4] = "486 SL",
971 [8] = "486 DX/4",
972 [9] = "486 DX/4-WB"
981 [4] = "Pentium MMX",
992 [4] = "Pentium II (Deschutes)",
1003 [0] = "Pentium 4 (Unknown)",
1004 [1] = "Pentium 4 (Willamette)",
1005 [2] = "Pentium 4 (Northwood)",
1006 [4] = "Pentium 4 (Foster)",
1007 [5] = "Pentium 4 (Foster)",