Lines Matching +full:0 +full:x86
45 sld_off = 0,
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
142 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
145 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
150 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
155 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
156 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
157 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
158 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
159 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
161 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
176 if (c->x86 != 6) in bad_spectre_microcode()
179 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { in bad_spectre_microcode()
191 struct cpu_signature csig = { 0 }; in intel_cpu_collect_info()
194 memset(uci, 0, sizeof(*uci)); in intel_cpu_collect_info()
196 eax = 0x00000001; in intel_cpu_collect_info()
197 ecx = 0; in intel_cpu_collect_info()
205 /* get processor flags from MSR 0x17 */ in intel_cpu_collect_info()
206 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); in intel_cpu_collect_info()
215 return 0; in intel_cpu_collect_info()
224 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
226 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { in early_init_intel()
227 c->cpuid_level = cpuid_eax(0); in early_init_intel()
232 if ((c->x86 == 0xf && c->x86_model >= 0x03) || in early_init_intel()
233 (c->x86 == 0x6 && c->x86_model >= 0x0e)) in early_init_intel()
236 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
263 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && in early_init_intel()
264 c->microcode < 0x20e) { in early_init_intel()
273 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
277 /* CPUID workaround for 0F33/0F34 CPU */ in early_init_intel()
278 if (c->x86 == 0xF && c->x86_model == 0x3 in early_init_intel()
279 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
295 if (c->x86 == 6) { in early_init_intel()
318 if (c->x86 == 6 && c->x86_model < 15) in early_init_intel()
325 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
340 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h in early_init_intel()
344 if (c->x86 == 5 && c->x86_model == 9) { in early_init_intel()
349 if (c->cpuid_level >= 0x00000001) { in early_init_intel()
352 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); in early_init_intel()
359 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); in early_init_intel()
368 if (detect_extended_topology_early(c) < 0) in early_init_intel()
388 boot_cpu_data.x86 == 6 && in ppro_with_ram_bug()
394 return 0; in ppro_with_ram_bug()
406 if (c->x86 == 5 && in intel_smp_check()
430 * have the F0 0F bug, which lets nonprivileged users lock up the in intel_workarounds()
435 if (c->x86 == 5 && c->x86_model < 9) { in intel_workarounds()
440 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); in intel_workarounds()
450 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
468 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { in intel_workarounds()
470 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { in intel_workarounds()
482 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
483 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
491 switch (c->x86) { in intel_workarounds()
530 #define MSR_IA32_TME_ACTIVATE 0x982
533 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
534 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
536 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
537 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
539 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
541 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
545 #define MKTME_ENABLED 0
553 int keyid_bits = 0, nr_keyids = 0; in detect_tme()
554 static u64 tme_activate_cpu0 = 0; in detect_tme()
561 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); in detect_tme()
562 pr_err_once("x86/tme: MKTME is not usable\n"); in detect_tme()
572 pr_info_once("x86/tme: not enabled by BIOS\n"); in detect_tme()
580 pr_info("x86/tme: enabled by BIOS\n"); in detect_tme()
584 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); in detect_tme()
588 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", in detect_tme()
596 pr_info_once("x86/mktme: enabled by BIOS\n"); in detect_tme()
597 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); in detect_tme()
599 pr_info_once("x86/mktme: disabled by BIOS\n"); in detect_tme()
632 this_cpu_write(msr_misc_features_shadow, 0); in init_intel_misc_features()
660 * let's use the legacy cpuid vector 0x1 and 0x4 for topology in init_intel()
674 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) in init_intel()
691 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && in init_intel()
695 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && in init_intel()
700 if (c->x86 == 15) in init_intel()
702 if (c->x86 == 6) in init_intel()
710 if (c->x86 == 6) { in init_intel()
716 if (l2 == 0) in init_intel()
725 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
739 if (c->x86 == 15) in init_intel()
741 if (c->x86 == 6) in init_intel()
770 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) in intel_size_cache()
777 if ((c->x86 == 5) && (c->x86_model == 9)) in intel_size_cache()
783 #define TLB_INST_4K 0x01
784 #define TLB_INST_4M 0x02
785 #define TLB_INST_2M_4M 0x03
787 #define TLB_INST_ALL 0x05
788 #define TLB_INST_1G 0x06
790 #define TLB_DATA_4K 0x11
791 #define TLB_DATA_4M 0x12
792 #define TLB_DATA_2M_4M 0x13
793 #define TLB_DATA_4K_4M 0x14
795 #define TLB_DATA_1G 0x16
797 #define TLB_DATA0_4K 0x21
798 #define TLB_DATA0_4M 0x22
799 #define TLB_DATA0_2M_4M 0x23
801 #define STLB_4K 0x41
802 #define STLB_4K_2M 0x42
805 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
806 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
807 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
808 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
809 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
810 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
811 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
812 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
813 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
814 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
815 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
816 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
817 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
818 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
819 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
820 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
821 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
822 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
823 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
824 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
825 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
826 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
827 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
828 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
829 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
830 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
831 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
832 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
833 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
834 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
835 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
836 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
837 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
838 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
839 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
840 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
841 { 0x00, 0, 0 }
847 if (desc == 0) in intel_tlb_lookup()
851 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
852 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
855 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
941 n = cpuid_eax(2) & 0xFF; in intel_detect_tlb()
943 for (i = 0 ; i < n ; i++) { in intel_detect_tlb()
944 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); in intel_detect_tlb()
947 for (j = 0 ; j < 3 ; j++) in intel_detect_tlb()
949 regs[j] = 0; in intel_detect_tlb()
951 /* Byte 0 is level count, not a descriptor */ in intel_detect_tlb()
964 [0] = "486 DX-25/33",
977 [0] = "Pentium 60/66 A-step",
989 [0] = "Pentium Pro A-step",
1003 [0] = "Pentium 4 (Unknown)",
1023 #define pr_fmt(fmt) "x86/split lock detection: " fmt
1051 ratelimit > 0 && ratelimit <= 1000) { in match_option()
1088 if (ret >= 0) { in sld_state_setup()
1089 for (i = 0; i < ARRAY_SIZE(sld_options); i++) { in sld_state_setup()
1169 return 0; in splitlock_cpu_offline()
1179 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n", in split_lock_warn()
1184 if (msleep_interruptible(10) > 0) in split_lock_warn()
1204 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n", in handle_guest_split_lock()
1208 current->thread.error_code = 0; in handle_guest_split_lock()
1259 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n", in handle_bus_lock()
1275 * - 0: CPU models that are known to have the per-core split-lock detection
1282 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1283 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1284 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1310 case 0: in split_lock_setup()
1341 "x86/splitlock", NULL, splitlock_cpu_offline) < 0) in sld_state_show()
1376 * a hybrid processor. If the processor is not hybrid, returns 0.
1381 return 0; in get_this_hybrid_cpu_type()
1383 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; in get_this_hybrid_cpu_type()