214 	[GDT_ENTRY_KERNEL32_CS]		= GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
215 	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
216 	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
217 	[GDT_ENTRY_DEFAULT_USER32_CS]	= GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
218 	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
219 	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
221 	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
222 	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
223 	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
224 	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
231 	[GDT_ENTRY_PNPBIOS_CS32]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
233 	[GDT_ENTRY_PNPBIOS_CS16]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
235 	[GDT_ENTRY_PNPBIOS_DS]		= GDT_ENTRY_INIT(0x0092, 0, 0xffff),
237 	[GDT_ENTRY_PNPBIOS_TS1]		= GDT_ENTRY_INIT(0x0092, 0, 0),
239 	[GDT_ENTRY_PNPBIOS_TS2]		= GDT_ENTRY_INIT(0x0092, 0, 0),
245 	[GDT_ENTRY_APMBIOS_BASE]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
247 	[GDT_ENTRY_APMBIOS_BASE+1]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
249 	[GDT_ENTRY_APMBIOS_BASE+2]	= GDT_ENTRY_INIT(0x4092, 0, 0xffff),
251 	[GDT_ENTRY_ESPFIX_SS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
252 	[GDT_ENTRY_PERCPU]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
266 		return 0;  in x86_nopcid_setup()
270 	return 0;  in x86_nopcid_setup()
283 		return 0;  in x86_noinvpcid_setup()
287 	return 0;  in x86_noinvpcid_setup()
316 		      "popl %0		\n\t"  in flag_is_changeable_p()
317 		      "movl %0, %1	\n\t"  in flag_is_changeable_p()
318 		      "xorl %2, %0	\n\t"  in flag_is_changeable_p()
319 		      "pushl %0		\n\t"  in flag_is_changeable_p()
322 		      "popl %0		\n\t"  in flag_is_changeable_p()
328 	return ((f1^f2) & flag) != 0;  in flag_is_changeable_p()
347 	lo |= 0x200000;  in squash_the_stupid_serial_number()
354 	c->cpuid_level = cpuid_eax(0);  in squash_the_stupid_serial_number()
359 	disable_x86_serial_nr = 0;  in x86_serial_nr_setup()
423 	unsigned long bits_missing = 0;  in native_write_cr0()
426 	asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");  in native_write_cr0()
442 	unsigned long bits_changed = 0;  in native_write_cr4()
445 	asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");  in native_write_cr4()
454 		WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",  in native_write_cr4()
513 		return 0;  in x86_nofsgsbase_setup()
575 	u64 msr = 0;  in ibt_save()
620 		wrmsrl(MSR_IA32_S_CET, 0);  in cet_disable()
635 	{ X86_FEATURE_MWAIT,		0x00000005 },
636 	{ X86_FEATURE_DCA,		0x00000009 },
637 	{ X86_FEATURE_XSAVE,		0x0000000d },
638 	{ 0, 0 }
651 		 * extended_extended_level is set to 0 if unavailable  in filter_cpuid_features()
656 		if (!((s32)df->level < 0 ?  in filter_cpuid_features()
665 		pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",  in filter_cpuid_features()
673  * in particular, if CPUID levels 0x80000002..4 are supported, this
709 	__loadsegment_simple(gs, 0);  in load_percpu_segment()
760 	if (c->extended_cpuid_level < 0x80000004)  in get_model_name()
764 	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);  in get_model_name()
765 	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);  in get_model_name()
766 	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);  in get_model_name()
767 	c->x86_model_id[48] = 0;  in get_model_name()
770 	p = q = s = &c->x86_model_id[0];  in get_model_name()
783 	*(s + 1) = '\0';  in get_model_name()
794 	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);  in detect_num_cpu_cores()
795 	if (eax & 0x1f)  in detect_num_cpu_cores()
805 	if (n >= 0x80000005) {  in cpu_detect_cache_sizes()
806 		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);  in cpu_detect_cache_sizes()
810 		c->x86_tlbsize = 0;  in cpu_detect_cache_sizes()
814 	if (n < 0x80000006)	/* Some chips just has a large L1. */  in cpu_detect_cache_sizes()
817 	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);  in cpu_detect_cache_sizes()
821 	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);  in cpu_detect_cache_sizes()
831 	if (l2size == 0)  in cpu_detect_cache_sizes()
876 	smp_num_siblings = (ebx & 0xff0000) >> 16;  in detect_ht_early()
880 	return 0;  in detect_ht_early()
888 	if (detect_ht_early(c) < 0)  in detect_ht()
910 	for (i = 0; i < X86_VENDOR_NUM; i++) {  in get_cpu_vendor()
914 		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||  in get_cpu_vendor()
934 	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,  in cpu_detect()
935 	      (unsigned int *)&c->x86_vendor_id[0],  in cpu_detect()
940 	/* Intel-defined flags: level 0x00000001 */  in cpu_detect()
941 	if (c->cpuid_level >= 0x00000001) {  in cpu_detect()
944 		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);  in cpu_detect()
950 			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;  in cpu_detect()
960 	for (i = 0; i < NCAPINTS + NBUGINTS; i++) {  in apply_forced_caps()
1011 	/* Intel-defined flags: level 0x00000001 */  in get_cpu_cap()
1012 	if (c->cpuid_level >= 0x00000001) {  in get_cpu_cap()
1013 		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1019 	/* Thermal and Power Management Leaf: level 0x00000006 (eax) */  in get_cpu_cap()
1020 	if (c->cpuid_level >= 0x00000006)  in get_cpu_cap()
1021 		c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);  in get_cpu_cap()
1023 	/* Additional Intel-defined flags: level 0x00000007 */  in get_cpu_cap()
1024 	if (c->cpuid_level >= 0x00000007) {  in get_cpu_cap()
1025 		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1032 			cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1037 	/* Extended state features: level 0x0000000d */  in get_cpu_cap()
1038 	if (c->cpuid_level >= 0x0000000d) {  in get_cpu_cap()
1039 		cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1044 	/* AMD-defined flags: level 0x80000001 */  in get_cpu_cap()
1045 	eax = cpuid_eax(0x80000000);  in get_cpu_cap()
1048 	if ((eax & 0xffff0000) == 0x80000000) {  in get_cpu_cap()
1049 		if (eax >= 0x80000001) {  in get_cpu_cap()
1050 			cpuid(0x80000001, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1057 	if (c->extended_cpuid_level >= 0x80000007) {  in get_cpu_cap()
1058 		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1064 	if (c->extended_cpuid_level >= 0x80000008) {  in get_cpu_cap()
1065 		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
1069 	if (c->extended_cpuid_level >= 0x8000000a)  in get_cpu_cap()
1070 		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);  in get_cpu_cap()
1072 	if (c->extended_cpuid_level >= 0x8000001f)  in get_cpu_cap()
1073 		c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);  in get_cpu_cap()
1090 	if (c->extended_cpuid_level >= 0x80000008) {  in get_cpu_address_sizes()
1091 		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);  in get_cpu_address_sizes()
1093 		c->x86_virt_bits = (eax >> 8) & 0xff;  in get_cpu_address_sizes()
1094 		c->x86_phys_bits = eax & 0xff;  in get_cpu_address_sizes()
1117 	for (i = 0; i < X86_VENDOR_NUM; i++)  in identify_cpu_without_cpuid()
1119 			c->x86_vendor_id[0] = 0;  in identify_cpu_without_cpuid()
1121 			if (c->x86_vendor_id[0]) {  in identify_cpu_without_cpuid()
1129 #define NO_SPECULATION		BIT(0)
1201 	/* AMD Family 0xf - 0x12 */
1202 	VULNWL_AMD(0x0f,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1203 	VULNWL_AMD(0x10,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1204 	VULNWL_AMD(0x11,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1205 	VULNWL_AMD(0x12,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1207 	/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1231 #define SRBDS		BIT(0)
1259 	VULNBL_INTEL_STEPPINGS(COMETLAKE_L,	X86_STEPPINGS(0x0, 0x0),	MMIO | RETBLEED),
1267 	VULNBL_AMD(0x15, RETBLEED),
1268 	VULNBL_AMD(0x16, RETBLEED),
1269 	VULNBL_AMD(0x17, RETBLEED),
1270 	VULNBL_HYGON(0x18, RETBLEED),
1283 	u64 ia32_cap = 0;  in x86_read_arch_cap_msr()
1334 	 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:  in cpu_set_bug_bits()
1429 	int arglen, taint = 0;  in cpu_parse_early_param()
1453 	if (arglen <= 0)  in cpu_parse_early_param()
1490 		for (bit = 0; bit < 32 * NCAPINTS; bit++) {  in cpu_parse_early_param()
1536 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));  in early_identify_cpu()
1537 	c->extended_cpuid_level = 0;  in early_identify_cpu()
1554 		c->cpu_index = 0;  in early_identify_cpu()
1602 	int count = 0;  in early_cpu_init()
1620 			for (j = 0; j < 2; j++) {  in early_cpu_init()
1652 	loadsegment(fs, 0);  in detect_null_seg_behavior()
1655 	return tmp == 0;  in detect_null_seg_behavior()
1665 	if (c->extended_cpuid_level >= 0x80000021 &&  in check_null_seg_clears_base()
1666 	    cpuid_eax(0x80000021) & BIT(6))  in check_null_seg_clears_base()
1683 	 * 0x18 is the respective family for Hygon.  in check_null_seg_clears_base()
1685 	if ((c->x86 == 0x17 || c->x86 == 0x18) &&  in check_null_seg_clears_base()
1695 	c->extended_cpuid_level = 0;  in generic_identify()
1712 	if (c->cpuid_level >= 0x00000001) {  in generic_identify()
1713 		c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;  in generic_identify()
1716 		c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);  in generic_identify()
1728 	 * systems that run Linux at CPL > 0 may or may not have the  in generic_identify()
1762 	c->logical_proc_id = 0;  in validate_apic_and_package_id()
1774 	c->x86_cache_size = 0;  in identify_cpu()
1776 	c->x86_model = c->x86_stepping = 0;	/* So far unknown... */  in identify_cpu()
1777 	c->x86_vendor_id[0] = '\0'; /* Unset */  in identify_cpu()
1778 	c->x86_model_id[0] = '\0';  /* Unset */  in identify_cpu()
1780 	c->x86_coreid_bits = 0;  in identify_cpu()
1781 	c->cu_id = 0xff;  in identify_cpu()
1793 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));  in identify_cpu()
1795 	memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));  in identify_cpu()
1807 	c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);  in identify_cpu()
1846 	if (!c->x86_model_id[0]) {  in identify_cpu()
1879 		for (i = 0; i < NCAPINTS; i++)  in identify_cpu()
1921 	wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);  in enable_sep_cpu()
1922 	wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);  in enable_sep_cpu()
1923 	wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);  in enable_sep_cpu()
1966 		if (c->cpuid_level >= 0)  in print_cpu_info()
1973 	if (c->x86_model_id[0])  in print_cpu_info()
1978 	pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);  in print_cpu_info()
1980 	if (c->x86_stepping || c->cpuid_level >= 0)  in print_cpu_info()
1981 		pr_cont(", stepping: 0x%x)\n", c->x86_stepping);  in print_cpu_info()
2031 	wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);  in syscall_init()
2049 	wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);  in syscall_init()
2050 	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);  in syscall_init()
2095 	for (i = 0; i < 8; i++) {  in clear_all_debug_regs()
2100 		set_debugreg(0, i);  in clear_all_debug_regs()
2138 		wrmsr(MSR_TSC_AUX, cpudata, 0);  in setup_getcpu()
2188 	tss->io_bitmap.prev_max = 0;  in tss_setup_io_bitmap()
2189 	tss->io_bitmap.prev_sequence = 0;  in tss_setup_io_bitmap()
2190 	memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));  in tss_setup_io_bitmap()
2195 	tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;  in tss_setup_io_bitmap()
2241 	if (this_cpu_read(numa_node) == 0 &&  in cpu_init()
2258 		loadsegment(fs, 0);  in cpu_init()
2259 		memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);  in cpu_init()
2262 		wrmsrl(MSR_FS_BASE, 0);  in cpu_init()
2263 		wrmsrl(MSR_KERNEL_GS_BASE, 0);  in cpu_init()
2321 	info.cpuid_level = cpuid_eax(0);  in microcode_check()