37  * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
44 	u32 gprs[8] = { 0 };  in rdmsrl_amd_safe()
47 	WARN_ONCE((boot_cpu_data.x86 != 0xf),  in rdmsrl_amd_safe()
51 	gprs[7] = 0x9c5a203a;  in rdmsrl_amd_safe()
55 	*p = gprs[0] | ((u64)gprs[2] << 32);  in rdmsrl_amd_safe()
62 	u32 gprs[8] = { 0 };  in wrmsrl_amd_safe()
64 	WARN_ONCE((boot_cpu_data.x86 != 0xf),  in wrmsrl_amd_safe()
67 	gprs[0] = (u32)val;  in wrmsrl_amd_safe()
70 	gprs[7] = 0x9c5a203a;  in wrmsrl_amd_safe()
103  * of the Elan at 0x000df000. Unfortunately, one of the Linux  in init_amd_k5()
107 #define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */  in init_amd_k5()
108 #define CBAR_ENB	(0x80000000)  in init_amd_k5()
109 #define CBAR_KEY	(0X000000CB)  in init_amd_k5()
112 			outl(0 | CBAR_KEY, CBAR);  in init_amd_k5()
125 		if (c->x86_model == 0) {  in init_amd_k6()
168 		if ((l&0x0000FFFF) == 0) {  in init_amd_k6()
170 			l = (1<<0)|((mbytes/4)<<1);  in init_amd_k6()
189 		if ((l&0xFFFF0000) == 0) {  in init_amd_k6()
217 	 * Bit 15 of Athlon specific MSR 15, needs to be 0  in init_amd_k7()
236 		if ((l & 0xfff00000) != 0x20000000) {  in init_amd_k7()
238 				l, ((l & 0x000fffff)|0x20000000));  in init_amd_k7()
239 			wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);  in init_amd_k7()
252 	if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||  in init_amd_k7()
257 	if ((c->x86_model == 7) && (c->x86_stepping == 0))  in init_amd_k7()
294 	for (i = apicid - 1; i >= 0; i--) {  in nearby_node()
310  * [0 .. cores_per_node - 1] range. Not really needed but
317 	if (c->x86 >= 0x17)  in legacy_fixup_core_id()
339 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);  in amd_get_topology()
341 		c->cpu_die_id  = ecx & 0xff;  in amd_get_topology()
343 		if (c->x86 == 0x15)  in amd_get_topology()
344 			c->cu_id = ebx & 0xff;  in amd_get_topology()
346 		if (c->x86 >= 0x17) {  in amd_get_topology()
347 			c->cpu_core_id = ebx & 0xff;  in amd_get_topology()
460 	if (c->extended_cpuid_level < 0x80000008)  in early_init_amd_mc()
463 	ecx = cpuid_ecx(0x80000008);  in early_init_amd_mc()
465 	c->x86_max_cores = (ecx & 0xff) + 1;  in early_init_amd_mc()
468 	bits = (ecx >> 12) & 0xF;  in early_init_amd_mc()
471 	if (bits == 0) {  in early_init_amd_mc()
484 		if (c->x86 > 0x10 ||  in bsp_init_amd()
485 		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {  in bsp_init_amd()
494 	if (c->x86 == 0x15) {  in bsp_init_amd()
498 		cpuid	 = cpuid_edx(0x80000005);  in bsp_init_amd()
499 		assoc	 = cpuid >> 16 & 0xff;  in bsp_init_amd()
515 		ecx = cpuid_ecx(0x8000001e);  in bsp_init_amd()
526 	    c->x86 >= 0x15 && c->x86 <= 0x17) {  in bsp_init_amd()
529 		switch (c->x86) {  in bsp_init_amd()
530 		case 0x15: bit = 54; break;  in bsp_init_amd()
531 		case 0x16: bit = 33; break;  in bsp_init_amd()
532 		case 0x17: bit = 10; break;  in bsp_init_amd()
578 		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;  in early_detect_mem_encrypt()
607 	if (c->x86 >= 0xf)  in early_init_amd()
633 	if (c->x86 == 5)  in early_init_amd()
641 	 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we  in early_init_amd()
646 		if (c->x86 > 0x16)  in early_init_amd()
648 		else if (c->x86 >= 0xf) {  in early_init_amd()
652 			val = read_pci_config(0, 24, 0, 0x68);  in early_init_amd()
653 			if ((val >> 17 & 0x3) == 0x3)  in early_init_amd()
667 	if (c->x86 == 0x16 && c->x86_model <= 0xf)  in early_init_amd()
682 	if (c->x86 == 0x15 &&  in early_init_amd()
683 	    (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&  in early_init_amd()
686 		if (msr_set_bit(0xc0011005, 54) > 0) {  in early_init_amd()
687 			rdmsrl(0xc0011005, value);  in early_init_amd()
696 		smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;  in early_init_amd()
706 	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)  in init_amd_k8()
711 	 * (model = 0x14) and later actually support it.  in init_amd_k8()
714 	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {  in init_amd_k8()
716 		if (!rdmsrl_amd_safe(0xc001100d, &value)) {  in init_amd_k8()
718 			wrmsrl_amd_safe(0xc001100d, value);  in init_amd_k8()
722 	if (!c->x86_model_id[0])  in init_amd_k8()
794 	return 0;  in rdrand_cmdline()
802 	 * suspend/resume is done by arch/x86/power/cpu.c, which is  in clear_rdrand_cpuid_bit()
848 	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {  in init_amd_bd()
849 		if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {  in init_amd_bd()
850 			value |= 0x1E;  in init_amd_bd()
901 		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to  in init_amd_zn()
905 		if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))  in init_amd_zn()
918 	clear_cpu_cap(c, 0*32+31);  in init_amd()
920 	if (c->x86 >= 0x10)  in init_amd()
927 	if (c->x86 < 6)  in init_amd()
930 	switch (c->x86) {  in init_amd()
934 	case 0xf:  init_amd_k8(c); break;  in init_amd()
935 	case 0x10: init_amd_gh(c); break;  in init_amd()
936 	case 0x12: init_amd_ln(c); break;  in init_amd()
937 	case 0x15: init_amd_bd(c); break;  in init_amd()
938 	case 0x16: init_amd_jg(c); break;  in init_amd()
939 	case 0x17: init_spectral_chicken(c);  in init_amd()
941 	case 0x19: init_amd_zn(c); break;  in init_amd()
948 	if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))  in init_amd()
974 	 * Family 0x12 and above processors have APIC timer  in init_amd()
977 	if (c->x86 > 0x11)  in init_amd()
1005 	if (c->x86 == 6) {  in amd_size_cache()
1007 		if (c->x86_model == 3 && c->x86_stepping == 0)  in amd_size_cache()
1011 			(c->x86_stepping == 0 || c->x86_stepping == 1))  in amd_size_cache()
1021 	u16 mask = 0xfff;  in cpu_detect_tlb_amd()
1023 	if (c->x86 < 0xf)  in cpu_detect_tlb_amd()
1026 	if (c->extended_cpuid_level < 0x80000006)  in cpu_detect_tlb_amd()
1029 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);  in cpu_detect_tlb_amd()
1036 	 * characteristics from the CPUID function 0x80000005 instead.  in cpu_detect_tlb_amd()
1038 	if (c->x86 == 0xf) {  in cpu_detect_tlb_amd()
1039 		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);  in cpu_detect_tlb_amd()
1040 		mask = 0xff;  in cpu_detect_tlb_amd()
1045 		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;  in cpu_detect_tlb_amd()
1055 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {  in cpu_detect_tlb_amd()
1058 			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);  in cpu_detect_tlb_amd()
1059 			tlb_lli_2m[ENTRIES] = eax & 0xff;  in cpu_detect_tlb_amd()
1106  *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1107  *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1108  *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1111 #define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
1112 #define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }
1115 #define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)
1116 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
1117 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
1120 	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1121 			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1124 	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1128 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
1136 	if (osvw_id >= 0 && osvw_id < 65536 &&  in cpu_has_amd_erratum()
1146 			return osvw_bits & (1ULL << (osvw_id & 0x3f));  in cpu_has_amd_erratum()
1153 		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&  in cpu_has_amd_erratum()
1167 	case 0:  in set_dr_addr_mask()
1168 		wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);  in set_dr_addr_mask()
1173 		wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);  in set_dr_addr_mask()
1184 	if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||  in amd_get_highest_perf()
1185 			       (c->x86_model >= 0x70 && c->x86_model < 0x80)))  in amd_get_highest_perf()
1188 	if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||  in amd_get_highest_perf()
1189 			       (c->x86_model >= 0x40 && c->x86_model < 0x70)))  in amd_get_highest_perf()