Lines Matching +full:level +full:- +full:triggered
1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
73 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
112 * Saved state during suspend/resume, or while enabling intr-remap.
145 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
150 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
183 * disable_ioapic_support() - disables ioapic support at runtime
189 noioapicreroute = -1; in disable_ioapic_support()
196 /* disable IO-APIC */ in parse_noapic()
209 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, in mp_save_irq()
210 m->srcbusirq, m->dstapic, m->dstirq); in mp_save_irq()
271 writel(vector, &io_apic->eoi); in io_apic_eoi()
277 writel(reg, &io_apic->index); in native_io_apic_read()
278 return readl(&io_apic->data); in native_io_apic_read()
286 writel(reg, &io_apic->index); in io_apic_write()
287 writel(value, &io_apic->data); in io_apic_write()
350 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
351 * shared ISA-space IRQs, so we have to support them. We are super
352 * fast in the common case, and fast for shared ISA-space IRQs.
360 for_each_irq_pin(entry, data->irq_2_pin) in __add_pin_to_irq_node()
361 if (entry->apic == apic && entry->pin == pin) in __add_pin_to_irq_node()
368 return -ENOMEM; in __add_pin_to_irq_node()
370 entry->apic = apic; in __add_pin_to_irq_node()
371 entry->pin = pin; in __add_pin_to_irq_node()
372 list_add_tail(&entry->list, &data->irq_2_pin); in __add_pin_to_irq_node()
381 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) in __remove_pin_from_irq()
382 if (entry->apic == apic && entry->pin == pin) { in __remove_pin_from_irq()
383 list_del(&entry->list); in __remove_pin_from_irq()
393 panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); in add_pin_to_irq_node()
405 for_each_irq_pin(entry, data->irq_2_pin) { in replace_pin_at_irq_node()
406 if (entry->apic == oldapic && entry->pin == oldpin) { in replace_pin_at_irq_node()
407 entry->apic = newapic; in replace_pin_at_irq_node()
408 entry->pin = newpin; in replace_pin_at_irq_node()
423 data->entry.masked = masked; in io_apic_modify_irq()
425 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_modify_irq()
426 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); in io_apic_modify_irq()
435 * Synchronize the IO-APIC and the CPU by doing in io_apic_sync()
436 * a dummy read from the IO-APIC in io_apic_sync()
440 io_apic = io_apic_base(entry->apic); in io_apic_sync()
441 readl(&io_apic->data); in io_apic_sync()
446 struct mp_chip_data *data = irq_data->chip_data; in mask_ioapic_irq()
461 struct mp_chip_data *data = irq_data->chip_data; in unmask_ioapic_irq()
470 * IO-APIC versions below 0x20 don't support EOI register.
475 * 30h-FFh Reserved
477 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
479 * use io-apic's of version 0x20.
481 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
483 * mode to edge and then back to level, with RTE being masked during this.
503 * Restore the previous level triggered entry. in __eoi_ioapic_pin()
515 for_each_irq_pin(entry, data->irq_2_pin) in eoi_ioapic_pin()
516 __eoi_ioapic_pin(entry->apic, entry->pin, vector); in eoi_ioapic_pin()
530 * Make sure the entry is masked and re-read the contents to check in clear_IO_APIC_pin()
531 * if it is a level triggered pin and if the remote-IRR is set. in clear_IO_APIC_pin()
543 * Make sure the trigger mode is set to level. Explicit EOI in clear_IO_APIC_pin()
544 * doesn't clear the remote-IRR if the trigger mode is not in clear_IO_APIC_pin()
545 * set to level. in clear_IO_APIC_pin()
557 * Clear the rest of the bits in the IO-APIC RTE except for the mask in clear_IO_APIC_pin()
577 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
578 * specific CPU-side IRQs.
583 [0 ... MAX_PIRQS - 1] = -1
594 "PIRQ redirection, working around broken MP-BIOS.\n"); in ioapic_pirq_setup()
601 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); in ioapic_pirq_setup()
605 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; in ioapic_pirq_setup()
614 * Saves all the IO-APIC RTE's
623 err = -ENOMEM; in save_ioapic_entries()
690 return -1; in find_irq_entry()
709 return -1; in find_isa_irq_pin()
733 return -1; in find_isa_irq_apic()
746 * Conforms to spec, ie. bus-type dependent polarity. PCI in irq_active_low()
763 * EISA Edge/Level control register, ELCR
777 * EISA interrupts are always active high and can be edge or level
778 * triggered depending on the ELCR value. If an interrupt is listed as
782 static bool eisa_irq_is_level(int idx, int bus, bool level) in eisa_irq_is_level() argument
787 return level; in eisa_irq_is_level()
791 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus); in eisa_irq_is_level()
795 static inline int eisa_irq_is_level(int idx, int bus, bool level) in eisa_irq_is_level() argument
797 return level; in eisa_irq_is_level()
804 bool level; in irq_is_level() local
807 * Determine IRQ trigger mode (edge or level sensitive): in irq_is_level()
812 * Conforms to spec, ie. bus-type dependent trigger in irq_is_level()
813 * mode. PCI defaults to level, ISA to edge. in irq_is_level()
815 level = !test_bit(bus, mp_bus_not_pci); in irq_is_level()
817 return eisa_irq_is_level(idx, bus, level); in irq_is_level()
821 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n"); in irq_is_level()
834 return -1; in __acpi_get_override_irq()
838 return -1; in __acpi_get_override_irq()
842 return -1; in __acpi_get_override_irq()
846 return -1; in __acpi_get_override_irq()
866 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_set_alloc_attr()
867 info->ioapic.node = node; in ioapic_set_alloc_attr()
868 info->ioapic.is_level = trigger; in ioapic_set_alloc_attr()
869 info->ioapic.active_low = polarity; in ioapic_set_alloc_attr()
870 info->ioapic.valid = 1; in ioapic_set_alloc_attr()
877 bool level, pol_low; in ioapic_copy_alloc_attr() local
880 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_copy_alloc_attr()
881 dst->devid = mpc_ioapic_id(ioapic_idx); in ioapic_copy_alloc_attr()
882 dst->ioapic.pin = pin; in ioapic_copy_alloc_attr()
883 dst->ioapic.valid = 1; in ioapic_copy_alloc_attr()
884 if (src && src->ioapic.valid) { in ioapic_copy_alloc_attr()
885 dst->ioapic.node = src->ioapic.node; in ioapic_copy_alloc_attr()
886 dst->ioapic.is_level = src->ioapic.is_level; in ioapic_copy_alloc_attr()
887 dst->ioapic.active_low = src->ioapic.active_low; in ioapic_copy_alloc_attr()
889 dst->ioapic.node = NUMA_NO_NODE; in ioapic_copy_alloc_attr()
890 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) { in ioapic_copy_alloc_attr()
891 dst->ioapic.is_level = level; in ioapic_copy_alloc_attr()
892 dst->ioapic.active_low = pol_low; in ioapic_copy_alloc_attr()
895 * PCI interrupts are always active low level in ioapic_copy_alloc_attr()
896 * triggered. in ioapic_copy_alloc_attr()
898 dst->ioapic.is_level = true; in ioapic_copy_alloc_attr()
899 dst->ioapic.active_low = true; in ioapic_copy_alloc_attr()
906 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE; in ioapic_alloc_attr_node()
909 static void mp_register_handler(unsigned int irq, bool level) in mp_register_handler() argument
914 if (level) { in mp_register_handler()
935 if (irq < nr_legacy_irqs() && data->count == 1) { in mp_check_pin_attr()
936 if (info->ioapic.is_level != data->is_level) in mp_check_pin_attr()
937 mp_register_handler(irq, info->ioapic.is_level); in mp_check_pin_attr()
938 data->entry.is_level = data->is_level = info->ioapic.is_level; in mp_check_pin_attr()
939 data->entry.active_low = data->active_low = info->ioapic.active_low; in mp_check_pin_attr()
942 return data->is_level == info->ioapic.is_level && in mp_check_pin_attr()
943 data->active_low == info->ioapic.active_low; in mp_check_pin_attr()
950 int irq = -1; in alloc_irq_from_domain()
956 * Dynamically allocate IRQ number for non-ISA IRQs in the first in alloc_irq_from_domain()
970 return -1; in alloc_irq_from_domain()
981 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
982 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
983 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
1001 if (irq_data && irq_data->parent_data) { in alloc_isa_irq_from_domain()
1003 return -EBUSY; in alloc_isa_irq_from_domain()
1004 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, in alloc_isa_irq_from_domain()
1005 info->ioapic.pin)) in alloc_isa_irq_from_domain()
1006 return -ENOMEM; in alloc_isa_irq_from_domain()
1008 info->flags |= X86_IRQ_ALLOC_LEGACY; in alloc_isa_irq_from_domain()
1013 data = irq_data->chip_data; in alloc_isa_irq_from_domain()
1014 data->isa_irq = true; in alloc_isa_irq_from_domain()
1031 return -ENOSYS; in mp_map_pin_to_irq()
1045 return -EINVAL; in mp_map_pin_to_irq()
1053 irq = -ENOENT; in mp_map_pin_to_irq()
1063 irq = -EBUSY; in mp_map_pin_to_irq()
1066 data->count++; in mp_map_pin_to_irq()
1089 if (pirq_entries[pin-16] != -1) { in pin_2_irq()
1090 if (!pirq_entries[pin-16]) { in pin_2_irq()
1092 "disabling PIRQ%d\n", pin-16); in pin_2_irq()
1094 int irq = pirq_entries[pin-16]; in pin_2_irq()
1096 "using PIRQ%d -> IRQ %d\n", in pin_2_irq()
1097 pin-16, irq); in pin_2_irq()
1113 return -ENODEV; in mp_map_gsi_to_irq()
1118 return -ENODEV; in mp_map_gsi_to_irq()
1128 if (!irq_data || !irq_data->domain) in mp_unmap_irq()
1131 data = irq_data->chip_data; in mp_unmap_irq()
1132 if (!data || data->isa_irq) in mp_unmap_irq()
1136 if (--data->count == 0) in mp_unmap_irq()
1147 int irq, i, best_ioapic = -1, best_idx = -1; in IO_APIC_get_PCI_irq_vector()
1150 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", in IO_APIC_get_PCI_irq_vector()
1155 return -1; in IO_APIC_get_PCI_irq_vector()
1187 * Use the first all-but-pin matching entry as a in IO_APIC_get_PCI_irq_vector()
1188 * best-guess fuzzy result for broken mptables. in IO_APIC_get_PCI_irq_vector()
1196 return -1; in IO_APIC_get_PCI_irq_vector()
1243 entry.is_level ? "level" : "edge ", in io_apic_print_entries()
1323 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", in print_IO_APICs()
1348 if (list_empty(&data->irq_2_pin)) in print_IO_APICs()
1352 for_each_irq_pin(entry, data->irq_2_pin) in print_IO_APICs()
1353 pr_cont("-> %d:%d", entry->apic, entry->pin); in print_IO_APICs()
1361 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1397 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { in enable_IO_APIC()
1410 * Do not trust the IO-APIC being empty at bootup in enable_IO_APIC()
1422 if (ioapic_i8259.pin != -1) { in native_restore_boot_irq_mode()
1436 * Add it to the IO-APIC irq-routing table: in native_restore_boot_irq_mode()
1442 disconnect_bsp_APIC(ioapic_i8259.pin != -1); in native_restore_boot_irq_mode()
1455 * function to set the IO-APIC physical IDs based on the
1473 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); in setup_ioapic_ids_from_mpc_nocheck()
1487 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1499 if (apic->check_apicid_used(&phys_id_present_map, in setup_ioapic_ids_from_mpc_nocheck()
1501 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1514 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), in setup_ioapic_ids_from_mpc_nocheck()
1540 "...changing IO-APIC physical APIC ID to %d ...", in setup_ioapic_ids_from_mpc_nocheck()
1602 } while ((now - start) < 40000000000ULL / HZ && in delay_with_tsc()
1627 * - timer IRQ defaults to IO-APIC IRQ
1628 * - if this function detects that timer IRQs are defunct, then we fall
1647 * ticks in a non-ExtINT mode. Also the local APIC in timer_irq_works()
1666 * Edge triggered needs to resend any interrupt
1672 * Starting up a edge-triggered IO-APIC interrupt is
1673 * nasty - we need to make sure that we get the edge.
1677 * This is not complete - we should be able to fake
1682 int was_pending = 0, irq = data->irq; in startup_ioapic_irq()
1687 legacy_pic->mask(irq); in startup_ioapic_irq()
1688 if (legacy_pic->irq_pending(irq)) in startup_ioapic_irq()
1691 __unmask_ioapic(data->chip_data); in startup_ioapic_irq()
1706 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_level_ack_pending()
1710 pin = entry->pin; in io_apic_level_ack_pending()
1711 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); in io_apic_level_ack_pending()
1739 * On rare occasions the broadcast level triggered ack gets in ioapic_finish_move()
1746 * - On any sane system the read of the ioapic will in ioapic_finish_move()
1749 * - We get to see if the ACK has actually been delivered. in ioapic_finish_move()
1763 if (!io_apic_level_ack_pending(data->chip_data)) in ioapic_finish_move()
1793 * chipsets). Under certain conditions a level-triggered interrupt is in ioapic_ack_level()
1794 * erroneously delivered as edge-triggered one but the respective IRR in ioapic_ack_level()
1803 * by setting the trigger mode to edge and then to level when the edge in ioapic_ack_level()
1805 * level-triggered interrupt. We mask the source for the time of the in ioapic_ack_level()
1806 * operation to prevent an edge-triggered interrupt escaping meanwhile. in ioapic_ack_level()
1807 * The idea is from Manfred Spraul. --macro in ioapic_ack_level()
1813 * level-triggered io-apic interrupt will be seen as an edge in ioapic_ack_level()
1815 * to be broadcasted to the IO-APIC's which will clear the remoteIRR in ioapic_ack_level()
1816 * corresponding to the level-triggered interrupt. Hence on IO-APIC's in ioapic_ack_level()
1818 * remote IRR and on IO-APIC's which don't have an EOI register, in ioapic_ack_level()
1819 * we use the above logic (mask+edge followed by unmask+level) from in ioapic_ack_level()
1822 i = cfg->vector; in ioapic_ack_level()
1833 * message via io-apic EOI register write or simulating it using in ioapic_ack_level()
1834 * mask+edge followed by unmask+level logic) manually when the in ioapic_ack_level()
1835 * level triggered interrupt is seen as the edge triggered interrupt in ioapic_ack_level()
1840 eoi_ioapic_pin(cfg->vector, irq_data->chip_data); in ioapic_ack_level()
1848 struct mp_chip_data *data = irq_data->chip_data; in ioapic_ir_ack_level()
1851 * Intr-remapping uses pin number as the virtual vector in ioapic_ir_ack_level()
1853 * intr-remapping table entry. Hence for the io-apic in ioapic_ir_ack_level()
1857 eoi_ioapic_pin(data->entry.vector, data); in ioapic_ir_ack_level()
1885 * - Real vector in ioapic_setup_msg_from_msi()
1886 * - DMAR/IR: 8bit subhandle (ioapic.pin) in ioapic_setup_msg_from_msi()
1887 * - AMD/IR: 8bit IRTE index in ioapic_setup_msg_from_msi()
1889 entry->vector = msg.arch_data.vector; in ioapic_setup_msg_from_msi()
1891 entry->delivery_mode = msg.arch_data.delivery_mode; in ioapic_setup_msg_from_msi()
1893 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical; in ioapic_setup_msg_from_msi()
1895 entry->ir_format = msg.arch_addr_lo.dmar_format; in ioapic_setup_msg_from_msi()
1897 * - DMAR/IR: index bit 0-14. in ioapic_setup_msg_from_msi()
1899 * - Virt: If the host supports x2apic without a virtualized IR in ioapic_setup_msg_from_msi()
1900 * unit then bit 0-6 of dmar_index_0_14 are providing bit in ioapic_setup_msg_from_msi()
1901 * 8-14 of the destination id. in ioapic_setup_msg_from_msi()
1903 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the in ioapic_setup_msg_from_msi()
1904 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7). in ioapic_setup_msg_from_msi()
1906 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14; in ioapic_setup_msg_from_msi()
1911 struct mp_chip_data *mpd = irqd->chip_data; in ioapic_configure_entry()
1914 ioapic_setup_msg_from_msi(irqd, &mpd->entry); in ioapic_configure_entry()
1916 for_each_irq_pin(entry, mpd->irq_2_pin) in ioapic_configure_entry()
1917 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); in ioapic_configure_entry()
1923 struct irq_data *parent = irq_data->parent_data; in ioapic_set_affinity()
1927 ret = parent->chip->irq_set_affinity(parent, mask, force); in ioapic_set_affinity()
1948 * Verify that the corresponding Remote-IRR bits are clear.
1954 struct mp_chip_data *mcd = irqd->chip_data; in ioapic_irq_get_chip_state()
1959 return -EINVAL; in ioapic_irq_get_chip_state()
1963 for_each_irq_pin(p, mcd->irq_2_pin) { in ioapic_irq_get_chip_state()
1964 rentry = __ioapic_read_entry(p->apic, p->pin); in ioapic_irq_get_chip_state()
1966 * The remote IRR is only valid in level trigger mode. It's in ioapic_irq_get_chip_state()
1967 * meaning is undefined for edge triggered interrupts and in ioapic_irq_get_chip_state()
1968 * irrelevant because the IO-APIC treats them as fire and in ioapic_irq_get_chip_state()
1981 .name = "IO-APIC",
1995 .name = "IR-IO-APIC",
2015 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { in init_IO_APIC_traps()
2018 * so default to an old-fashioned 8259 in init_IO_APIC_traps()
2022 legacy_pic->make_irq(irq); in init_IO_APIC_traps()
2031 * The local APIC irq-chip implementation:
2056 .name = "local-APIC",
2073 * cycles as some i82489DX-based boards have glue logic that keeps the
2074 * 8259A interrupt line asserted until INTA. --macro
2084 if (pin == -1) { in unlock_ExtINT_logic()
2089 if (apic == -1) { in unlock_ExtINT_logic()
2118 while (i-- > 0) { in unlock_ExtINT_logic()
2121 i -= 10; in unlock_ExtINT_logic()
2132 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2142 int irq = -1; in mp_alloc_timer_irq()
2170 struct mp_chip_data *data = irq_data->chip_data; in check_timer()
2184 legacy_pic->mask(0); in check_timer()
2191 * watchdog as that APIC treats NMIs as level-triggered. in check_timer()
2196 legacy_pic->init(1); in check_timer()
2205 cfg->vector, apic1, pin1, apic2, pin2); in check_timer()
2214 if (pin1 == -1) { in check_timer()
2215 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); in check_timer()
2219 } else if (pin2 == -1) { in check_timer()
2224 if (pin1 != -1) { in check_timer()
2231 * so only need to unmask if it is level-trigger in check_timer()
2232 * do we really have level trigger timer? in check_timer()
2236 if (idx != -1 && irq_is_level(idx)) in check_timer()
2246 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); in check_timer()
2249 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " in check_timer()
2250 "8254 timer not connected to IO-APIC\n"); in check_timer()
2262 legacy_pic->unmask(0); in check_timer()
2270 legacy_pic->mask(0); in check_timer()
2279 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ in check_timer()
2280 legacy_pic->unmask(0); in check_timer()
2286 legacy_pic->mask(0); in check_timer()
2287 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); in check_timer()
2293 legacy_pic->init(0); in check_timer()
2294 legacy_pic->make_irq(0); in check_timer()
2296 legacy_pic->unmask(0); in check_timer()
2307 "Perhaps problem with the pre-enabled x2apic mode\n" in check_timer()
2308 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); in check_timer()
2309 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " in check_timer()
2324 * interrupt, that is edge-triggered and unmasked by default. We
2330 * it anyway. --macro
2339 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; in mp_irqdomain_create()
2344 if (cfg->type == IOAPIC_DOMAIN_INVALID) in mp_irqdomain_create()
2348 if (cfg->dev) { in mp_irqdomain_create()
2349 fn = of_node_to_fwnode(cfg->dev); in mp_irqdomain_create()
2351 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic)); in mp_irqdomain_create()
2353 return -ENOMEM; in mp_irqdomain_create()
2362 if (!cfg->dev) in mp_irqdomain_create()
2364 return -ENODEV; in mp_irqdomain_create()
2367 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops, in mp_irqdomain_create()
2370 if (!ip->irqdomain) { in mp_irqdomain_create()
2372 if (!cfg->dev) in mp_irqdomain_create()
2374 return -ENOMEM; in mp_irqdomain_create()
2377 ip->irqdomain->parent = parent; in mp_irqdomain_create()
2379 if (cfg->type == IOAPIC_DOMAIN_LEGACY || in mp_irqdomain_create()
2380 cfg->type == IOAPIC_DOMAIN_STRICT) in mp_irqdomain_create()
2382 gsi_cfg->gsi_end + 1); in mp_irqdomain_create()
2390 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode; in ioapic_destroy_irqdomain()
2394 if (!cfg->dev) in ioapic_destroy_irqdomain()
2409 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); in setup_IO_APIC()
2414 * Set up IO-APIC IRQ routing. in setup_IO_APIC()
2510 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full in io_apic_get_unique_id()
2515 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); in io_apic_get_unique_id()
2531 if (apic->check_apicid_used(&apic_id_map, apic_id)) { in io_apic_get_unique_id()
2534 if (!apic->check_apicid_used(&apic_id_map, i)) in io_apic_get_unique_id()
2547 apic->apicid_to_cpu_present(apic_id, &tmp); in io_apic_get_unique_id()
2562 return -1; in io_apic_get_unique_id()
2707 "WARNING: bogus zero IO-APIC " in io_apic_init_mappings()
2732 ioapic_res->start = ioapic_phys; in io_apic_init_mappings()
2733 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; in io_apic_init_mappings()
2761 return -1; in mp_find_ioapic()
2766 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) in mp_find_ioapic()
2771 return -1; in mp_find_ioapic()
2779 return -1; in mp_find_ioapic_pin()
2782 if (WARN_ON(gsi > gsi_cfg->gsi_end)) in mp_find_ioapic_pin()
2783 return -1; in mp_find_ioapic_pin()
2785 return gsi - gsi_cfg->gsi_base; in mp_find_ioapic_pin()
2798 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { in bad_ioapic_register()
2819 * mp_register_ioapic - Register an IOAPIC device
2835 return -EINVAL; in mp_register_ioapic()
2841 return -EEXIST; in mp_register_ioapic()
2848 return -ENOSPC; in mp_register_ioapic()
2858 return -ENODEV; in mp_register_ioapic()
2865 * Build basic GSI lookup table to facilitate gsi->io_apic lookups in mp_register_ioapic()
2869 gsi_end = gsi_base + entries - 1; in mp_register_ioapic()
2872 if ((gsi_base >= gsi_cfg->gsi_base && in mp_register_ioapic()
2873 gsi_base <= gsi_cfg->gsi_end) || in mp_register_ioapic()
2874 (gsi_end >= gsi_cfg->gsi_base && in mp_register_ioapic()
2875 gsi_end <= gsi_cfg->gsi_end)) { in mp_register_ioapic()
2876 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", in mp_register_ioapic()
2878 gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2880 return -ENOSPC; in mp_register_ioapic()
2884 gsi_cfg->gsi_base = gsi_base; in mp_register_ioapic()
2885 gsi_cfg->gsi_end = gsi_end; in mp_register_ioapic()
2898 return -ENOMEM; in mp_register_ioapic()
2903 if (gsi_cfg->gsi_end >= gsi_top) in mp_register_ioapic()
2904 gsi_top = gsi_cfg->gsi_end + 1; in mp_register_ioapic()
2911 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", in mp_register_ioapic()
2914 gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2931 return -ENODEV; in mp_unregister_ioapic()
2941 if (data && data->count) { in mp_unregister_ioapic()
2944 return -EBUSY; in mp_unregister_ioapic()
2975 if (info && info->ioapic.valid) { in mp_irqdomain_get_attr()
2976 data->is_level = info->ioapic.is_level; in mp_irqdomain_get_attr()
2977 data->active_low = info->ioapic.active_low; in mp_irqdomain_get_attr()
2978 } else if (__acpi_get_override_irq(gsi, &data->is_level, in mp_irqdomain_get_attr()
2979 &data->active_low) < 0) { in mp_irqdomain_get_attr()
2980 /* PCI interrupts are always active low level triggered. */ in mp_irqdomain_get_attr()
2981 data->is_level = true; in mp_irqdomain_get_attr()
2982 data->active_low = true; in mp_irqdomain_get_attr()
2987 * Configure the I/O-APIC specific fields in the routing entry.
2989 * This is important to setup the I/O-APIC specific bits (is_level,
2991 * provide the routing information and is oblivious of the I/O-APIC
3000 struct IO_APIC_route_entry *entry = &data->entry; in mp_preconfigure_entry()
3003 entry->is_level = data->is_level; in mp_preconfigure_entry()
3004 entry->active_low = data->active_low; in mp_preconfigure_entry()
3006 * Mask level triggered irqs. Edge triggered irqs are masked in mp_preconfigure_entry()
3009 entry->masked = data->is_level; in mp_preconfigure_entry()
3022 return -EINVAL; in mp_irqdomain_alloc()
3025 return -EINVAL; in mp_irqdomain_alloc()
3028 pin = info->ioapic.pin; in mp_irqdomain_alloc()
3030 return -EEXIST; in mp_irqdomain_alloc()
3034 return -ENOMEM; in mp_irqdomain_alloc()
3042 INIT_LIST_HEAD(&data->irq_2_pin); in mp_irqdomain_alloc()
3043 irq_data->hwirq = info->ioapic.pin; in mp_irqdomain_alloc()
3044 irq_data->chip = (domain->parent == x86_vector_domain) ? in mp_irqdomain_alloc()
3046 irq_data->chip_data = data; in mp_irqdomain_alloc()
3052 mp_register_handler(virq, data->is_level); in mp_irqdomain_alloc()
3056 legacy_pic->mask(virq); in mp_irqdomain_alloc()
3060 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n", in mp_irqdomain_alloc()
3062 data->is_level, data->active_low); in mp_irqdomain_alloc()
3074 if (irq_data && irq_data->chip_data) { in mp_irqdomain_free()
3075 data = irq_data->chip_data; in mp_irqdomain_free()
3077 (int)irq_data->hwirq); in mp_irqdomain_free()
3078 WARN_ON(!list_empty(&data->irq_2_pin)); in mp_irqdomain_free()
3079 kfree(irq_data->chip_data); in mp_irqdomain_free()
3100 (int)irq_data->hwirq); in mp_irqdomain_deactivate()
3105 return (int)(long)domain->host_data; in mp_irqdomain_ioapic_idx()