Lines Matching +full:0 +full:x180000
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
24 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
25 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
26 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
27 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
28 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
29 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
30 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
31 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
32 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
33 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
34 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
35 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
36 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
37 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
38 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
58 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
121 { 0x00, 0x18, 0x20 },
122 { 0xff, 0x00, 0x20 },
123 { 0xfe, 0x00, 0x20 },
172 err = pci_write_config_dword(root, 0x60, address); in __amd_smn_rw()
174 pr_warn("Error programming SMN address 0x%x.\n", address); in __amd_smn_rw()
178 err = (write ? pci_write_config_dword(root, 0x64, *value) in __amd_smn_rw()
179 : pci_read_config_dword(root, 0x64, value)); in __amd_smn_rw()
181 pr_warn("Error %s SMN address 0x%x.\n", in __amd_smn_rw()
211 u16 roots_per_misc = 0; in amd_cache_northbridges()
212 u16 misc_count = 0; in amd_cache_northbridges()
213 u16 root_count = 0; in amd_cache_northbridges()
217 return 0; in amd_cache_northbridges()
257 for (i = 0; i < amd_northbridges.num; i++) { in amd_cache_northbridges()
284 if (!cpuid_edx(0x80000006)) in amd_cache_northbridges()
285 return 0; in amd_cache_northbridges()
289 * limitations because of E382 and E388 on family 0x10. in amd_cache_northbridges()
291 if (boot_cpu_data.x86 == 0x10 && in amd_cache_northbridges()
292 boot_cpu_data.x86_model >= 0x8 && in amd_cache_northbridges()
293 (boot_cpu_data.x86_model > 0x9 || in amd_cache_northbridges()
294 boot_cpu_data.x86_stepping >= 0x1)) in amd_cache_northbridges()
297 if (boot_cpu_data.x86 == 0x15) in amd_cache_northbridges()
300 /* L3 cache partitioning is supported on family 0x15 */ in amd_cache_northbridges()
301 if (boot_cpu_data.x86 == 0x15) in amd_cache_northbridges()
304 return 0; in amd_cache_northbridges()
315 u32 vendor = device & 0xffff; in early_is_amd_nb()
342 if (boot_cpu_data.x86 < 0x10) in amd_get_mmconfig_range()
369 return 0; in amd_get_subcaches()
371 pci_read_config_dword(link, 0x1d4, &mask); in amd_get_subcaches()
373 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf; in amd_get_subcaches()
383 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) in amd_set_subcaches()
387 if (reset == 0) { in amd_set_subcaches()
388 pci_read_config_dword(nb->link, 0x1d4, &reset); in amd_set_subcaches()
389 pci_read_config_dword(nb->misc, 0x1b8, &ban); in amd_set_subcaches()
390 ban &= 0x180000; in amd_set_subcaches()
394 if (mask != 0xf) { in amd_set_subcaches()
395 pci_read_config_dword(nb->misc, 0x1b8, ®); in amd_set_subcaches()
396 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); in amd_set_subcaches()
401 mask |= (0xf ^ (1 << cuid)) << 26; in amd_set_subcaches()
403 pci_write_config_dword(nb->link, 0x1d4, mask); in amd_set_subcaches()
406 pci_read_config_dword(nb->link, 0x1d4, ®); in amd_set_subcaches()
408 pci_read_config_dword(nb->misc, 0x1b8, ®); in amd_set_subcaches()
409 reg &= ~0x180000; in amd_set_subcaches()
410 pci_write_config_dword(nb->misc, 0x1b8, reg | ban); in amd_set_subcaches()
413 return 0; in amd_set_subcaches()
430 for (i = 0; i != amd_northbridges.num; i++) in amd_cache_gart()
431 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]); in amd_cache_gart()
450 flushed = 0; in amd_flush_garts()
451 for (i = 0; i < amd_northbridges.num; i++) { in amd_flush_garts()
452 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c, in amd_flush_garts()
456 for (i = 0; i < amd_northbridges.num; i++) { in amd_flush_garts()
461 0x9c, &w); in amd_flush_garts()
475 #define MSR_AMD64_IC_CFG 0xC0011021 in __fix_erratum_688()
487 if (boot_cpu_data.x86 != 0x14) in fix_erratum_688()
493 F4 = node_to_amd_nb(0)->link; in fix_erratum_688()
497 if (pci_read_config_dword(F4, 0x164, &val)) in fix_erratum_688()
503 on_each_cpu(__fix_erratum_688, NULL, 0); in fix_erratum_688()
515 return 0; in init_amd_nbs()