Lines Matching +full:ssc +full:- +full:internal
1 /* SPDX-License-Identifier: GPL-2.0 */
16 * perf-MSRs are not shared and every thread has its
17 * own perf-MSRs set)
21 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
25 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
207 * non-HT machines (on HT machines we count TS events in p4_default_cccr_conf()
304 * processor builds (family 0FH, models 01H-02H). These MSRs
613 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
822 * Notes on internal configuration of ESCR+CCCR tuples
846 * -----------
847 * 0-6: P4_PEBS_METRIC enum
848 * 7-11: reserved
850 * 13-15: reserved (ESCR select)
851 * 16-17: Active Thread
854 * 20-23: Threshold
859 * 28-29: reserved
864 * ------------
870 * 5-8: Tag Value
871 * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
872 * 25-30: enum P4_EVENTS