Lines Matching +full:0 +full:x8000000a
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
38 #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
39 #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
40 #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
41 #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
42 #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
43 #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
44 #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
46 #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
47 #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
48 #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
49 #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
50 #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
51 #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
52 #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
53 #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
54 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
56 #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
58 #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
80 #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
102 #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
160 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
161 #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
190 * CPUID levels like 0x6, 0xA etc, word 7.
194 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */
228 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
243 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
244 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
245 #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */
276 /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
277 #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */
285 * CPUID levels like 0xf, etc.
289 #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
311 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
315 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
316 #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
333 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
334 #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
346 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
347 #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
364 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
387 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
388 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
392 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
418 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
419 #define X86_FEATURE_SME (19*32+ 0) /* AMD Secure Memory Encryption */
431 #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */