Lines Matching defs:cpu_hw_events
229 struct cpu_hw_events { struct
233 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
234 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
235 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
236 int enabled;
238 int n_events; /* the # of events in the below arrays */
239 int n_added; /* the # last events in the below arrays;
241 int n_txn; /* the # last events in the below arrays;
243 int n_txn_pair;
244 int n_txn_metric;
245 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
246 u64 tags[X86_PMC_IDX_MAX];
248 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
249 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
251 int n_excl; /* the number of exclusive events */
253 unsigned int txn_flags;
254 int is_fake;
259 struct debug_store *ds;
260 void *ds_pebs_vaddr;
261 void *ds_bts_vaddr;
262 u64 pebs_enabled;
263 int n_pebs;
264 int n_large_pebs;
265 int n_pebs_via_pt;
266 int pebs_output;
269 u64 pebs_data_cfg;
270 u64 active_pebs_data_cfg;
271 int pebs_record_size;
274 u64 fixed_ctrl_val;
275 u64 active_fixed_ctrl_val;
280 int lbr_users;
281 int lbr_pebs_users;
282 struct perf_branch_stack lbr_stack;
283 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
284 union {
288 u64 br_sel;
289 void *last_task_ctx;
290 int last_log_id;
291 int lbr_select;
292 void *lbr_xsave;
297 u64 intel_ctrl_guest_mask;
298 u64 intel_ctrl_host_mask;
299 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
304 u64 intel_cp_status;
310 struct intel_shared_regs *shared_regs;
314 struct event_constraint *constraint_list; /* in enable order */
315 struct intel_excl_cntrs *excl_cntrs;
316 int excl_thread_id; /* 0 or 1 */
321 u64 tfa_shadow;
327 int n_metric;
332 struct amd_nb *amd_nb;
333 int brs_active; /* BRS is enabled */
336 u64 perf_ctr_virt_mask;
337 int n_pair; /* Large increment events */
339 void *kfree_on_online[X86_PERF_KFREE_MAX];
341 struct pmu *pmu;