Lines Matching +full:1 +full:c
57 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
216 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
270 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
274 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
315 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
378 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
387 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
388 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
421 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
447 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
471 [ C(L1D ) ] = {
472 [ C(OP_READ) ] = {
473 [ C(RESULT_ACCESS) ] = 0x81d0,
474 [ C(RESULT_MISS) ] = 0xe124,
476 [ C(OP_WRITE) ] = {
477 [ C(RESULT_ACCESS) ] = 0x82d0,
480 [ C(L1I ) ] = {
481 [ C(OP_READ) ] = {
482 [ C(RESULT_MISS) ] = 0xe424,
484 [ C(OP_WRITE) ] = {
485 [ C(RESULT_ACCESS) ] = -1,
486 [ C(RESULT_MISS) ] = -1,
489 [ C(LL ) ] = {
490 [ C(OP_READ) ] = {
491 [ C(RESULT_ACCESS) ] = 0x12a,
492 [ C(RESULT_MISS) ] = 0x12a,
494 [ C(OP_WRITE) ] = {
495 [ C(RESULT_ACCESS) ] = 0x12a,
496 [ C(RESULT_MISS) ] = 0x12a,
499 [ C(DTLB) ] = {
500 [ C(OP_READ) ] = {
501 [ C(RESULT_ACCESS) ] = 0x81d0,
502 [ C(RESULT_MISS) ] = 0xe12,
504 [ C(OP_WRITE) ] = {
505 [ C(RESULT_ACCESS) ] = 0x82d0,
506 [ C(RESULT_MISS) ] = 0xe13,
509 [ C(ITLB) ] = {
510 [ C(OP_READ) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = 0xe11,
514 [ C(OP_WRITE) ] = {
515 [ C(RESULT_ACCESS) ] = -1,
516 [ C(RESULT_MISS) ] = -1,
518 [ C(OP_PREFETCH) ] = {
519 [ C(RESULT_ACCESS) ] = -1,
520 [ C(RESULT_MISS) ] = -1,
523 [ C(BPU ) ] = {
524 [ C(OP_READ) ] = {
525 [ C(RESULT_ACCESS) ] = 0x4c4,
526 [ C(RESULT_MISS) ] = 0x4c5,
528 [ C(OP_WRITE) ] = {
529 [ C(RESULT_ACCESS) ] = -1,
530 [ C(RESULT_MISS) ] = -1,
532 [ C(OP_PREFETCH) ] = {
533 [ C(RESULT_ACCESS) ] = -1,
534 [ C(RESULT_MISS) ] = -1,
537 [ C(NODE) ] = {
538 [ C(OP_READ) ] = {
539 [ C(RESULT_ACCESS) ] = 0x12a,
540 [ C(RESULT_MISS) ] = 0x12a,
550 [ C(LL ) ] = {
551 [ C(OP_READ) ] = {
552 [ C(RESULT_ACCESS) ] = 0x10001,
553 [ C(RESULT_MISS) ] = 0x3fbfc00001,
555 [ C(OP_WRITE) ] = {
556 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
557 [ C(RESULT_MISS) ] = 0x3f3fc00002,
560 [ C(NODE) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = 0x10c000001,
563 [ C(RESULT_MISS) ] = 0x3fb3000001,
578 #define SKL_DEMAND_RFO BIT_ULL(1)
617 [ C(L1D ) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
620 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
624 [ C(RESULT_MISS) ] = 0x0,
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x0,
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
645 [ C(LL ) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
648 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
652 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0,
656 [ C(RESULT_MISS) ] = 0x0,
659 [ C(DTLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
662 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
666 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = 0x0,
670 [ C(RESULT_MISS) ] = 0x0,
673 [ C(ITLB) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
676 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
687 [ C(BPU ) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
690 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
701 [ C(NODE) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
704 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
708 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
722 [ C(LL ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
726 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
733 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
737 [ C(OP_PREFETCH) ] = {
738 [ C(RESULT_ACCESS) ] = 0x0,
739 [ C(RESULT_MISS) ] = 0x0,
742 [ C(NODE) ] = {
743 [ C(OP_READ) ] = {
744 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
746 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
749 [ C(OP_WRITE) ] = {
750 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
752 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
755 [ C(OP_PREFETCH) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0,
757 [ C(RESULT_MISS) ] = 0x0,
762 #define SNB_DMND_DATA_RD (1ULL << 0)
763 #define SNB_DMND_RFO (1ULL << 1)
764 #define SNB_DMND_IFETCH (1ULL << 2)
765 #define SNB_DMND_WB (1ULL << 3)
766 #define SNB_PF_DATA_RD (1ULL << 4)
767 #define SNB_PF_RFO (1ULL << 5)
768 #define SNB_PF_IFETCH (1ULL << 6)
769 #define SNB_LLC_DATA_RD (1ULL << 7)
770 #define SNB_LLC_RFO (1ULL << 8)
771 #define SNB_LLC_IFETCH (1ULL << 9)
772 #define SNB_BUS_LOCKS (1ULL << 10)
773 #define SNB_STRM_ST (1ULL << 11)
774 #define SNB_OTHER (1ULL << 15)
775 #define SNB_RESP_ANY (1ULL << 16)
776 #define SNB_NO_SUPP (1ULL << 17)
777 #define SNB_LLC_HITM (1ULL << 18)
778 #define SNB_LLC_HITE (1ULL << 19)
779 #define SNB_LLC_HITS (1ULL << 20)
780 #define SNB_LLC_HITF (1ULL << 21)
781 #define SNB_LOCAL (1ULL << 22)
783 #define SNB_SNP_NONE (1ULL << 31)
784 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
785 #define SNB_SNP_MISS (1ULL << 33)
786 #define SNB_NO_FWD (1ULL << 34)
787 #define SNB_SNP_FWD (1ULL << 35)
788 #define SNB_HITM (1ULL << 36)
789 #define SNB_NON_DRAM (1ULL << 37)
810 [ C(LL ) ] = {
811 [ C(OP_READ) ] = {
812 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
813 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
815 [ C(OP_WRITE) ] = {
816 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
817 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
819 [ C(OP_PREFETCH) ] = {
820 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
821 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
824 [ C(NODE) ] = {
825 [ C(OP_READ) ] = {
826 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
827 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
829 [ C(OP_WRITE) ] = {
830 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
831 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
833 [ C(OP_PREFETCH) ] = {
834 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
835 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
845 [ C(L1D) ] = {
846 [ C(OP_READ) ] = {
847 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
848 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
850 [ C(OP_WRITE) ] = {
851 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
852 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
854 [ C(OP_PREFETCH) ] = {
855 [ C(RESULT_ACCESS) ] = 0x0,
856 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
859 [ C(L1I ) ] = {
860 [ C(OP_READ) ] = {
861 [ C(RESULT_ACCESS) ] = 0x0,
862 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
864 [ C(OP_WRITE) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
868 [ C(OP_PREFETCH) ] = {
869 [ C(RESULT_ACCESS) ] = 0x0,
870 [ C(RESULT_MISS) ] = 0x0,
873 [ C(LL ) ] = {
874 [ C(OP_READ) ] = {
876 [ C(RESULT_ACCESS) ] = 0x01b7,
878 [ C(RESULT_MISS) ] = 0x01b7,
880 [ C(OP_WRITE) ] = {
882 [ C(RESULT_ACCESS) ] = 0x01b7,
884 [ C(RESULT_MISS) ] = 0x01b7,
886 [ C(OP_PREFETCH) ] = {
888 [ C(RESULT_ACCESS) ] = 0x01b7,
890 [ C(RESULT_MISS) ] = 0x01b7,
893 [ C(DTLB) ] = {
894 [ C(OP_READ) ] = {
895 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
896 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
898 [ C(OP_WRITE) ] = {
899 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
900 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
902 [ C(OP_PREFETCH) ] = {
903 [ C(RESULT_ACCESS) ] = 0x0,
904 [ C(RESULT_MISS) ] = 0x0,
907 [ C(ITLB) ] = {
908 [ C(OP_READ) ] = {
909 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
910 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
912 [ C(OP_WRITE) ] = {
913 [ C(RESULT_ACCESS) ] = -1,
914 [ C(RESULT_MISS) ] = -1,
916 [ C(OP_PREFETCH) ] = {
917 [ C(RESULT_ACCESS) ] = -1,
918 [ C(RESULT_MISS) ] = -1,
921 [ C(BPU ) ] = {
922 [ C(OP_READ) ] = {
923 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
924 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
926 [ C(OP_WRITE) ] = {
927 [ C(RESULT_ACCESS) ] = -1,
928 [ C(RESULT_MISS) ] = -1,
930 [ C(OP_PREFETCH) ] = {
931 [ C(RESULT_ACCESS) ] = -1,
932 [ C(RESULT_MISS) ] = -1,
935 [ C(NODE) ] = {
936 [ C(OP_READ) ] = {
937 [ C(RESULT_ACCESS) ] = 0x01b7,
938 [ C(RESULT_MISS) ] = 0x01b7,
940 [ C(OP_WRITE) ] = {
941 [ C(RESULT_ACCESS) ] = 0x01b7,
942 [ C(RESULT_MISS) ] = 0x01b7,
944 [ C(OP_PREFETCH) ] = {
945 [ C(RESULT_ACCESS) ] = 0x01b7,
946 [ C(RESULT_MISS) ] = 0x01b7,
962 #define HSW_DEMAND_RFO BIT_ULL(1)
1001 [ C(L1D ) ] = {
1002 [ C(OP_READ) ] = {
1003 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1004 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1006 [ C(OP_WRITE) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1008 [ C(RESULT_MISS) ] = 0x0,
1010 [ C(OP_PREFETCH) ] = {
1011 [ C(RESULT_ACCESS) ] = 0x0,
1012 [ C(RESULT_MISS) ] = 0x0,
1015 [ C(L1I ) ] = {
1016 [ C(OP_READ) ] = {
1017 [ C(RESULT_ACCESS) ] = 0x0,
1018 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1020 [ C(OP_WRITE) ] = {
1021 [ C(RESULT_ACCESS) ] = -1,
1022 [ C(RESULT_MISS) ] = -1,
1024 [ C(OP_PREFETCH) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x0,
1026 [ C(RESULT_MISS) ] = 0x0,
1029 [ C(LL ) ] = {
1030 [ C(OP_READ) ] = {
1031 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1032 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1034 [ C(OP_WRITE) ] = {
1035 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1036 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1038 [ C(OP_PREFETCH) ] = {
1039 [ C(RESULT_ACCESS) ] = 0x0,
1040 [ C(RESULT_MISS) ] = 0x0,
1043 [ C(DTLB) ] = {
1044 [ C(OP_READ) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1046 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1048 [ C(OP_WRITE) ] = {
1049 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1050 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1052 [ C(OP_PREFETCH) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x0,
1054 [ C(RESULT_MISS) ] = 0x0,
1057 [ C(ITLB) ] = {
1058 [ C(OP_READ) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1060 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1062 [ C(OP_WRITE) ] = {
1063 [ C(RESULT_ACCESS) ] = -1,
1064 [ C(RESULT_MISS) ] = -1,
1066 [ C(OP_PREFETCH) ] = {
1067 [ C(RESULT_ACCESS) ] = -1,
1068 [ C(RESULT_MISS) ] = -1,
1071 [ C(BPU ) ] = {
1072 [ C(OP_READ) ] = {
1073 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1074 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1076 [ C(OP_WRITE) ] = {
1077 [ C(RESULT_ACCESS) ] = -1,
1078 [ C(RESULT_MISS) ] = -1,
1080 [ C(OP_PREFETCH) ] = {
1081 [ C(RESULT_ACCESS) ] = -1,
1082 [ C(RESULT_MISS) ] = -1,
1085 [ C(NODE) ] = {
1086 [ C(OP_READ) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1088 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1090 [ C(OP_WRITE) ] = {
1091 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1092 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1094 [ C(OP_PREFETCH) ] = {
1095 [ C(RESULT_ACCESS) ] = 0x0,
1096 [ C(RESULT_MISS) ] = 0x0,
1106 [ C(LL ) ] = {
1107 [ C(OP_READ) ] = {
1108 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1110 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1113 [ C(OP_WRITE) ] = {
1114 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1116 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1119 [ C(OP_PREFETCH) ] = {
1120 [ C(RESULT_ACCESS) ] = 0x0,
1121 [ C(RESULT_MISS) ] = 0x0,
1124 [ C(NODE) ] = {
1125 [ C(OP_READ) ] = {
1126 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1129 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1133 [ C(OP_WRITE) ] = {
1134 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1137 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1141 [ C(OP_PREFETCH) ] = {
1142 [ C(RESULT_ACCESS) ] = 0x0,
1143 [ C(RESULT_MISS) ] = 0x0,
1153 [ C(L1D) ] = {
1154 [ C(OP_READ) ] = {
1155 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1156 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1158 [ C(OP_WRITE) ] = {
1159 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1160 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1162 [ C(OP_PREFETCH) ] = {
1163 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1164 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1167 [ C(L1I ) ] = {
1168 [ C(OP_READ) ] = {
1169 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1170 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1172 [ C(OP_WRITE) ] = {
1173 [ C(RESULT_ACCESS) ] = -1,
1174 [ C(RESULT_MISS) ] = -1,
1176 [ C(OP_PREFETCH) ] = {
1177 [ C(RESULT_ACCESS) ] = 0x0,
1178 [ C(RESULT_MISS) ] = 0x0,
1181 [ C(LL ) ] = {
1182 [ C(OP_READ) ] = {
1184 [ C(RESULT_ACCESS) ] = 0x01b7,
1186 [ C(RESULT_MISS) ] = 0x01b7,
1192 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = 0x01b7,
1196 [ C(RESULT_MISS) ] = 0x01b7,
1198 [ C(OP_PREFETCH) ] = {
1200 [ C(RESULT_ACCESS) ] = 0x01b7,
1202 [ C(RESULT_MISS) ] = 0x01b7,
1205 [ C(DTLB) ] = {
1206 [ C(OP_READ) ] = {
1207 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1208 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1210 [ C(OP_WRITE) ] = {
1211 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1212 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1214 [ C(OP_PREFETCH) ] = {
1215 [ C(RESULT_ACCESS) ] = 0x0,
1216 [ C(RESULT_MISS) ] = 0x0,
1219 [ C(ITLB) ] = {
1220 [ C(OP_READ) ] = {
1221 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1222 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1224 [ C(OP_WRITE) ] = {
1225 [ C(RESULT_ACCESS) ] = -1,
1226 [ C(RESULT_MISS) ] = -1,
1228 [ C(OP_PREFETCH) ] = {
1229 [ C(RESULT_ACCESS) ] = -1,
1230 [ C(RESULT_MISS) ] = -1,
1233 [ C(BPU ) ] = {
1234 [ C(OP_READ) ] = {
1235 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1236 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1238 [ C(OP_WRITE) ] = {
1239 [ C(RESULT_ACCESS) ] = -1,
1240 [ C(RESULT_MISS) ] = -1,
1242 [ C(OP_PREFETCH) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1247 [ C(NODE) ] = {
1248 [ C(OP_READ) ] = {
1249 [ C(RESULT_ACCESS) ] = 0x01b7,
1250 [ C(RESULT_MISS) ] = 0x01b7,
1252 [ C(OP_WRITE) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x01b7,
1254 [ C(RESULT_MISS) ] = 0x01b7,
1256 [ C(OP_PREFETCH) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x01b7,
1258 [ C(RESULT_MISS) ] = 0x01b7,
1268 #define NHM_DMND_DATA_RD (1 << 0)
1269 #define NHM_DMND_RFO (1 << 1)
1270 #define NHM_DMND_IFETCH (1 << 2)
1271 #define NHM_DMND_WB (1 << 3)
1272 #define NHM_PF_DATA_RD (1 << 4)
1273 #define NHM_PF_DATA_RFO (1 << 5)
1274 #define NHM_PF_IFETCH (1 << 6)
1275 #define NHM_OFFCORE_OTHER (1 << 7)
1276 #define NHM_UNCORE_HIT (1 << 8)
1277 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1278 #define NHM_OTHER_CORE_HITM (1 << 10)
1280 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1281 #define NHM_REMOTE_DRAM (1 << 13)
1282 #define NHM_LOCAL_DRAM (1 << 14)
1283 #define NHM_NON_DRAM (1 << 15)
1301 [ C(LL ) ] = {
1302 [ C(OP_READ) ] = {
1303 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1304 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1306 [ C(OP_WRITE) ] = {
1307 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1308 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1310 [ C(OP_PREFETCH) ] = {
1311 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1312 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1315 [ C(NODE) ] = {
1316 [ C(OP_READ) ] = {
1317 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1318 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1320 [ C(OP_WRITE) ] = {
1321 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1322 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1324 [ C(OP_PREFETCH) ] = {
1325 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1326 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1336 [ C(L1D) ] = {
1337 [ C(OP_READ) ] = {
1338 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1339 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1341 [ C(OP_WRITE) ] = {
1342 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1343 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1345 [ C(OP_PREFETCH) ] = {
1346 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1347 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1350 [ C(L1I ) ] = {
1351 [ C(OP_READ) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1353 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1355 [ C(OP_WRITE) ] = {
1356 [ C(RESULT_ACCESS) ] = -1,
1357 [ C(RESULT_MISS) ] = -1,
1359 [ C(OP_PREFETCH) ] = {
1360 [ C(RESULT_ACCESS) ] = 0x0,
1361 [ C(RESULT_MISS) ] = 0x0,
1364 [ C(LL ) ] = {
1365 [ C(OP_READ) ] = {
1367 [ C(RESULT_ACCESS) ] = 0x01b7,
1369 [ C(RESULT_MISS) ] = 0x01b7,
1375 [ C(OP_WRITE) ] = {
1377 [ C(RESULT_ACCESS) ] = 0x01b7,
1379 [ C(RESULT_MISS) ] = 0x01b7,
1381 [ C(OP_PREFETCH) ] = {
1383 [ C(RESULT_ACCESS) ] = 0x01b7,
1385 [ C(RESULT_MISS) ] = 0x01b7,
1388 [ C(DTLB) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1391 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1395 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0x0,
1399 [ C(RESULT_MISS) ] = 0x0,
1402 [ C(ITLB) ] = {
1403 [ C(OP_READ) ] = {
1404 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1405 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1407 [ C(OP_WRITE) ] = {
1408 [ C(RESULT_ACCESS) ] = -1,
1409 [ C(RESULT_MISS) ] = -1,
1411 [ C(OP_PREFETCH) ] = {
1412 [ C(RESULT_ACCESS) ] = -1,
1413 [ C(RESULT_MISS) ] = -1,
1416 [ C(BPU ) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1419 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = -1,
1423 [ C(RESULT_MISS) ] = -1,
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1430 [ C(NODE) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x01b7,
1433 [ C(RESULT_MISS) ] = 0x01b7,
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = 0x01b7,
1437 [ C(RESULT_MISS) ] = 0x01b7,
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = 0x01b7,
1441 [ C(RESULT_MISS) ] = 0x01b7,
1451 [ C(L1D) ] = {
1452 [ C(OP_READ) ] = {
1453 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1454 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1456 [ C(OP_WRITE) ] = {
1457 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1458 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1460 [ C(OP_PREFETCH) ] = {
1461 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1462 [ C(RESULT_MISS) ] = 0,
1465 [ C(L1I ) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1468 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = -1,
1472 [ C(RESULT_MISS) ] = -1,
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1479 [ C(LL ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1482 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1486 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1493 [ C(DTLB) ] = {
1494 [ C(OP_READ) ] = {
1495 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1496 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1498 [ C(OP_WRITE) ] = {
1499 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1500 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1502 [ C(OP_PREFETCH) ] = {
1503 [ C(RESULT_ACCESS) ] = 0,
1504 [ C(RESULT_MISS) ] = 0,
1507 [ C(ITLB) ] = {
1508 [ C(OP_READ) ] = {
1509 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1510 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1512 [ C(OP_WRITE) ] = {
1513 [ C(RESULT_ACCESS) ] = -1,
1514 [ C(RESULT_MISS) ] = -1,
1516 [ C(OP_PREFETCH) ] = {
1517 [ C(RESULT_ACCESS) ] = -1,
1518 [ C(RESULT_MISS) ] = -1,
1521 [ C(BPU ) ] = {
1522 [ C(OP_READ) ] = {
1523 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1524 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1526 [ C(OP_WRITE) ] = {
1527 [ C(RESULT_ACCESS) ] = -1,
1528 [ C(RESULT_MISS) ] = -1,
1530 [ C(OP_PREFETCH) ] = {
1531 [ C(RESULT_ACCESS) ] = -1,
1532 [ C(RESULT_MISS) ] = -1,
1542 [ C(L1D) ] = {
1543 [ C(OP_READ) ] = {
1544 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1545 [ C(RESULT_MISS) ] = 0,
1547 [ C(OP_WRITE) ] = {
1548 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1549 [ C(RESULT_MISS) ] = 0,
1551 [ C(OP_PREFETCH) ] = {
1552 [ C(RESULT_ACCESS) ] = 0x0,
1553 [ C(RESULT_MISS) ] = 0,
1556 [ C(L1I ) ] = {
1557 [ C(OP_READ) ] = {
1558 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1559 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1561 [ C(OP_WRITE) ] = {
1562 [ C(RESULT_ACCESS) ] = -1,
1563 [ C(RESULT_MISS) ] = -1,
1565 [ C(OP_PREFETCH) ] = {
1566 [ C(RESULT_ACCESS) ] = 0,
1567 [ C(RESULT_MISS) ] = 0,
1570 [ C(LL ) ] = {
1571 [ C(OP_READ) ] = {
1572 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1573 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1575 [ C(OP_WRITE) ] = {
1576 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1577 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1579 [ C(OP_PREFETCH) ] = {
1580 [ C(RESULT_ACCESS) ] = 0,
1581 [ C(RESULT_MISS) ] = 0,
1584 [ C(DTLB) ] = {
1585 [ C(OP_READ) ] = {
1586 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1587 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1589 [ C(OP_WRITE) ] = {
1590 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1591 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1593 [ C(OP_PREFETCH) ] = {
1594 [ C(RESULT_ACCESS) ] = 0,
1595 [ C(RESULT_MISS) ] = 0,
1598 [ C(ITLB) ] = {
1599 [ C(OP_READ) ] = {
1600 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1601 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1603 [ C(OP_WRITE) ] = {
1604 [ C(RESULT_ACCESS) ] = -1,
1605 [ C(RESULT_MISS) ] = -1,
1607 [ C(OP_PREFETCH) ] = {
1608 [ C(RESULT_ACCESS) ] = -1,
1609 [ C(RESULT_MISS) ] = -1,
1612 [ C(BPU ) ] = {
1613 [ C(OP_READ) ] = {
1614 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1615 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1617 [ C(OP_WRITE) ] = {
1618 [ C(RESULT_ACCESS) ] = -1,
1619 [ C(RESULT_MISS) ] = -1,
1621 [ C(OP_PREFETCH) ] = {
1622 [ C(RESULT_ACCESS) ] = -1,
1623 [ C(RESULT_MISS) ] = -1,
1672 [ C(LL ) ] = {
1673 [ C(OP_READ) ] = {
1674 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1675 [ C(RESULT_MISS) ] = 0,
1677 [ C(OP_WRITE) ] = {
1678 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1679 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1681 [ C(OP_PREFETCH) ] = {
1682 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1683 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1693 [ C(L1D) ] = {
1694 [ C(OP_READ) ] = {
1695 [ C(RESULT_ACCESS) ] = 0,
1696 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1698 [ C(OP_WRITE) ] = {
1699 [ C(RESULT_ACCESS) ] = 0,
1700 [ C(RESULT_MISS) ] = 0,
1702 [ C(OP_PREFETCH) ] = {
1703 [ C(RESULT_ACCESS) ] = 0,
1704 [ C(RESULT_MISS) ] = 0,
1707 [ C(L1I ) ] = {
1708 [ C(OP_READ) ] = {
1709 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1710 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1712 [ C(OP_WRITE) ] = {
1713 [ C(RESULT_ACCESS) ] = -1,
1714 [ C(RESULT_MISS) ] = -1,
1716 [ C(OP_PREFETCH) ] = {
1717 [ C(RESULT_ACCESS) ] = 0,
1718 [ C(RESULT_MISS) ] = 0,
1721 [ C(LL ) ] = {
1722 [ C(OP_READ) ] = {
1724 [ C(RESULT_ACCESS) ] = 0x01b7,
1725 [ C(RESULT_MISS) ] = 0,
1727 [ C(OP_WRITE) ] = {
1729 [ C(RESULT_ACCESS) ] = 0x01b7,
1731 [ C(RESULT_MISS) ] = 0x01b7,
1733 [ C(OP_PREFETCH) ] = {
1735 [ C(RESULT_ACCESS) ] = 0x01b7,
1737 [ C(RESULT_MISS) ] = 0x01b7,
1740 [ C(DTLB) ] = {
1741 [ C(OP_READ) ] = {
1742 [ C(RESULT_ACCESS) ] = 0,
1743 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1745 [ C(OP_WRITE) ] = {
1746 [ C(RESULT_ACCESS) ] = 0,
1747 [ C(RESULT_MISS) ] = 0,
1749 [ C(OP_PREFETCH) ] = {
1750 [ C(RESULT_ACCESS) ] = 0,
1751 [ C(RESULT_MISS) ] = 0,
1754 [ C(ITLB) ] = {
1755 [ C(OP_READ) ] = {
1756 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1757 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1759 [ C(OP_WRITE) ] = {
1760 [ C(RESULT_ACCESS) ] = -1,
1761 [ C(RESULT_MISS) ] = -1,
1763 [ C(OP_PREFETCH) ] = {
1764 [ C(RESULT_ACCESS) ] = -1,
1765 [ C(RESULT_MISS) ] = -1,
1768 [ C(BPU ) ] = {
1769 [ C(OP_READ) ] = {
1770 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1771 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1773 [ C(OP_WRITE) ] = {
1774 [ C(RESULT_ACCESS) ] = -1,
1775 [ C(RESULT_MISS) ] = -1,
1777 [ C(OP_PREFETCH) ] = {
1778 [ C(RESULT_ACCESS) ] = -1,
1779 [ C(RESULT_MISS) ] = -1,
1813 #define GLM_DEMAND_RFO BIT_ULL(1)
1827 [C(L1D)] = {
1828 [C(OP_READ)] = {
1829 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1830 [C(RESULT_MISS)] = 0x0,
1832 [C(OP_WRITE)] = {
1833 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1834 [C(RESULT_MISS)] = 0x0,
1836 [C(OP_PREFETCH)] = {
1837 [C(RESULT_ACCESS)] = 0x0,
1838 [C(RESULT_MISS)] = 0x0,
1841 [C(L1I)] = {
1842 [C(OP_READ)] = {
1843 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1844 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1846 [C(OP_WRITE)] = {
1847 [C(RESULT_ACCESS)] = -1,
1848 [C(RESULT_MISS)] = -1,
1850 [C(OP_PREFETCH)] = {
1851 [C(RESULT_ACCESS)] = 0x0,
1852 [C(RESULT_MISS)] = 0x0,
1855 [C(LL)] = {
1856 [C(OP_READ)] = {
1857 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1858 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1860 [C(OP_WRITE)] = {
1861 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1862 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1864 [C(OP_PREFETCH)] = {
1865 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1866 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1869 [C(DTLB)] = {
1870 [C(OP_READ)] = {
1871 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1872 [C(RESULT_MISS)] = 0x0,
1874 [C(OP_WRITE)] = {
1875 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1876 [C(RESULT_MISS)] = 0x0,
1878 [C(OP_PREFETCH)] = {
1879 [C(RESULT_ACCESS)] = 0x0,
1880 [C(RESULT_MISS)] = 0x0,
1883 [C(ITLB)] = {
1884 [C(OP_READ)] = {
1885 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1886 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1888 [C(OP_WRITE)] = {
1889 [C(RESULT_ACCESS)] = -1,
1890 [C(RESULT_MISS)] = -1,
1892 [C(OP_PREFETCH)] = {
1893 [C(RESULT_ACCESS)] = -1,
1894 [C(RESULT_MISS)] = -1,
1897 [C(BPU)] = {
1898 [C(OP_READ)] = {
1899 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1900 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1902 [C(OP_WRITE)] = {
1903 [C(RESULT_ACCESS)] = -1,
1904 [C(RESULT_MISS)] = -1,
1906 [C(OP_PREFETCH)] = {
1907 [C(RESULT_ACCESS)] = -1,
1908 [C(RESULT_MISS)] = -1,
1917 [C(LL)] = {
1918 [C(OP_READ)] = {
1919 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1921 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1924 [C(OP_WRITE)] = {
1925 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1927 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1930 [C(OP_PREFETCH)] = {
1931 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1933 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1943 [C(L1D)] = {
1944 [C(OP_READ)] = {
1945 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1946 [C(RESULT_MISS)] = 0x0,
1948 [C(OP_WRITE)] = {
1949 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1950 [C(RESULT_MISS)] = 0x0,
1952 [C(OP_PREFETCH)] = {
1953 [C(RESULT_ACCESS)] = 0x0,
1954 [C(RESULT_MISS)] = 0x0,
1957 [C(L1I)] = {
1958 [C(OP_READ)] = {
1959 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1960 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1962 [C(OP_WRITE)] = {
1963 [C(RESULT_ACCESS)] = -1,
1964 [C(RESULT_MISS)] = -1,
1966 [C(OP_PREFETCH)] = {
1967 [C(RESULT_ACCESS)] = 0x0,
1968 [C(RESULT_MISS)] = 0x0,
1971 [C(LL)] = {
1972 [C(OP_READ)] = {
1973 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1974 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1976 [C(OP_WRITE)] = {
1977 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1978 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1980 [C(OP_PREFETCH)] = {
1981 [C(RESULT_ACCESS)] = 0x0,
1982 [C(RESULT_MISS)] = 0x0,
1985 [C(DTLB)] = {
1986 [C(OP_READ)] = {
1987 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1988 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1990 [C(OP_WRITE)] = {
1991 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1992 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1994 [C(OP_PREFETCH)] = {
1995 [C(RESULT_ACCESS)] = 0x0,
1996 [C(RESULT_MISS)] = 0x0,
1999 [C(ITLB)] = {
2000 [C(OP_READ)] = {
2001 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2002 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2004 [C(OP_WRITE)] = {
2005 [C(RESULT_ACCESS)] = -1,
2006 [C(RESULT_MISS)] = -1,
2008 [C(OP_PREFETCH)] = {
2009 [C(RESULT_ACCESS)] = -1,
2010 [C(RESULT_MISS)] = -1,
2013 [C(BPU)] = {
2014 [C(OP_READ)] = {
2015 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2016 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2018 [C(OP_WRITE)] = {
2019 [C(RESULT_ACCESS)] = -1,
2020 [C(RESULT_MISS)] = -1,
2022 [C(OP_PREFETCH)] = {
2023 [C(RESULT_ACCESS)] = -1,
2024 [C(RESULT_MISS)] = -1,
2033 [C(LL)] = {
2034 [C(OP_READ)] = {
2035 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2037 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2040 [C(OP_WRITE)] = {
2041 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2043 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2046 [C(OP_PREFETCH)] = {
2047 [C(RESULT_ACCESS)] = 0x0,
2048 [C(RESULT_MISS)] = 0x0,
2065 [C(LL)] = {
2066 [C(OP_READ)] = {
2067 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2069 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2072 [C(OP_WRITE)] = {
2073 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2075 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2078 [C(OP_PREFETCH)] = {
2079 [C(RESULT_ACCESS)] = 0x0,
2080 [C(RESULT_MISS)] = 0x0,
2142 [C(LL)] = {
2143 [C(OP_READ)] = {
2144 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2145 [C(RESULT_MISS)] = 0,
2147 [C(OP_WRITE)] = {
2148 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2149 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2151 [C(OP_PREFETCH)] = {
2152 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2153 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2297 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; in intel_pmu_nhm_workaround()
2307 * A) To reduce MSR operations, we don't run step 1) as they in intel_pmu_nhm_workaround()
2311 * C) With step 5), we do clear only when the PERFEVTSELx is in intel_pmu_nhm_workaround()
2454 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_disable_event()
2458 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_disable_event()
2581 * may be reduced from 1 to 0. If so, the bad_spec event value in __icl_update_topdown_event()
2601 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { in update_saved_topdown_regs()
2633 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { in intel_update_topdown_event()
2677 x86_pmu.num_topdown_events - 1); in icl_update_topdown_event()
2777 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_enable_event()
2781 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_enable_event()
3087 WARN(1, "perfevents: irq loop stuck!\n"); in intel_pmu_handle_irq()
3138 struct event_constraint *c = &vlbr_constraint; in intel_vlbr_constraints() local
3140 if (unlikely(constraint_match(c, event->hw.config))) { in intel_vlbr_constraints()
3141 event->hw.flags |= c->flags; in intel_vlbr_constraints()
3142 return c; in intel_vlbr_constraints()
3197 struct event_constraint *c = &emptyconstraint; in __intel_shared_reg_get_constraints() local
3240 reg->alloc = 1; in __intel_shared_reg_get_constraints()
3254 c = NULL; in __intel_shared_reg_get_constraints()
3264 return c; in __intel_shared_reg_get_constraints()
3297 struct event_constraint *c = NULL, *d; in intel_shared_regs_constraints() local
3302 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); in intel_shared_regs_constraints()
3303 if (c == &emptyconstraint) in intel_shared_regs_constraints()
3304 return c; in intel_shared_regs_constraints()
3311 c = d; in intel_shared_regs_constraints()
3314 return c; in intel_shared_regs_constraints()
3322 struct event_constraint *c; in x86_get_event_constraints() local
3325 for_each_event_constraint(c, event_constraints) { in x86_get_event_constraints()
3326 if (constraint_match(c, event->hw.config)) { in x86_get_event_constraints()
3327 event->hw.flags |= c->flags; in x86_get_event_constraints()
3328 return c; in x86_get_event_constraints()
3340 struct event_constraint *c; in __intel_get_event_constraints() local
3342 c = intel_vlbr_constraints(event); in __intel_get_event_constraints()
3343 if (c) in __intel_get_event_constraints()
3344 return c; in __intel_get_event_constraints()
3346 c = intel_bts_constraints(event); in __intel_get_event_constraints()
3347 if (c) in __intel_get_event_constraints()
3348 return c; in __intel_get_event_constraints()
3350 c = intel_shared_regs_constraints(cpuc, event); in __intel_get_event_constraints()
3351 if (c) in __intel_get_event_constraints()
3352 return c; in __intel_get_event_constraints()
3354 c = intel_pebs_constraints(event); in __intel_get_event_constraints()
3355 if (c) in __intel_get_event_constraints()
3356 return c; in __intel_get_event_constraints()
3394 struct event_constraint *c = cpuc->event_constraint[idx]; in intel_commit_scheduling() local
3404 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) in intel_commit_scheduling()
3411 if (c->flags & PERF_X86_EVENT_EXCL) in intel_commit_scheduling()
3445 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) in dyn_constraint() argument
3449 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { in dyn_constraint()
3461 *cx = *c; in dyn_constraint()
3467 c = cx; in dyn_constraint()
3470 return c; in dyn_constraint()
3475 int idx, struct event_constraint *c) in intel_get_excl_constraints() argument
3487 return c; in intel_get_excl_constraints()
3493 return c; in intel_get_excl_constraints()
3503 c = dyn_constraint(cpuc, c, idx); in intel_get_excl_constraints()
3515 xlo = &excl_cntrs->states[tid ^ 1]; in intel_get_excl_constraints()
3521 is_excl = c->flags & PERF_X86_EVENT_EXCL; in intel_get_excl_constraints()
3525 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); in intel_get_excl_constraints()
3536 w = c->weight; in intel_get_excl_constraints()
3537 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { in intel_get_excl_constraints()
3544 __clear_bit(i, c->idxmsk); in intel_get_excl_constraints()
3554 __clear_bit(i, c->idxmsk); in intel_get_excl_constraints()
3566 c = &emptyconstraint; in intel_get_excl_constraints()
3568 c->weight = w; in intel_get_excl_constraints()
3570 return c; in intel_get_excl_constraints()
3695 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3723 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
3744 * only programmed on counter 1, but that seems like an in intel_pebs_aliases_precdist()
3747 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3819 ((x86_pmu.num_topdown_events - 1) << 8))
4198 struct event_constraint *c; in hsw_get_event_constraints() local
4200 c = intel_get_event_constraints(cpuc, idx, event); in hsw_get_event_constraints()
4204 if (c->idxmsk64 & (1U << 2)) in hsw_get_event_constraints()
4209 return c; in hsw_get_event_constraints()
4231 struct event_constraint *c; in spr_get_event_constraints() local
4233 c = icl_get_event_constraints(cpuc, idx, event); in spr_get_event_constraints()
4243 if (c->idxmsk64 & BIT_ULL(0)) in spr_get_event_constraints()
4249 return c; in spr_get_event_constraints()
4256 struct event_constraint *c; in glp_get_event_constraints() local
4262 c = intel_get_event_constraints(cpuc, idx, event); in glp_get_event_constraints()
4264 return c; in glp_get_event_constraints()
4271 struct event_constraint *c; in tnt_get_event_constraints() local
4273 c = intel_get_event_constraints(cpuc, idx, event); in tnt_get_event_constraints()
4287 return c; in tnt_get_event_constraints()
4296 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); in tfa_get_event_constraints() local
4301 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { in tfa_get_event_constraints()
4302 c = dyn_constraint(cpuc, c, idx); in tfa_get_event_constraints()
4303 c->idxmsk64 &= ~(1ULL << 3); in tfa_get_event_constraints()
4304 c->weight--; in tfa_get_event_constraints()
4307 return c; in tfa_get_event_constraints()
4321 WARN_ON(1); in adl_get_event_constraints()
4334 WARN_ON(1); in adl_hw_config()
4420 regs->core_id = -1; in allocate_shared_regs()
4427 struct intel_excl_cntrs *c; in allocate_excl_cntrs() local
4429 c = kzalloc_node(sizeof(struct intel_excl_cntrs), in allocate_excl_cntrs()
4431 if (c) { in allocate_excl_cntrs()
4432 raw_spin_lock_init(&c->lock); in allocate_excl_cntrs()
4433 c->core_id = -1; in allocate_excl_cntrs()
4435 return c; in allocate_excl_cntrs()
4513 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { in init_hybrid_pmu()
4567 if (x86_pmu.version > 1) in intel_pmu_cpu_starting()
4585 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); in intel_pmu_cpu_starting()
4613 struct intel_excl_cntrs *c; in intel_pmu_cpu_starting() local
4616 c = sibling->excl_cntrs; in intel_pmu_cpu_starting()
4617 if (c && c->core_id == core_id) { in intel_pmu_cpu_starting()
4618 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; in intel_pmu_cpu_starting()
4619 cpuc->excl_cntrs = c; in intel_pmu_cpu_starting()
4621 cpuc->excl_thread_id = 1; in intel_pmu_cpu_starting()
4632 struct intel_excl_cntrs *c; in free_excl_cntrs() local
4634 c = cpuc->excl_cntrs; in free_excl_cntrs()
4635 if (c) { in free_excl_cntrs()
4636 if (c->core_id == -1 || --c->refcnt == 0) in free_excl_cntrs()
4637 kfree(c); in free_excl_cntrs()
4656 if (pc->core_id == -1 || --pc->refcnt == 0) in intel_cpuc_finish()
4770 .apic = 1,
4775 * so we install an artificial 1<<31 period regardless of
4778 .max_period = (1ULL<<31) - 1,
4788 * together with PMU version 1 and thus be using core_pmu with
4823 .apic = 1,
4827 * so we install an artificial 1<<31 period regardless of
4830 .max_period = (1ULL << 31) - 1,
4867 .attr_freeze_on_smi = 1,
4898 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4899 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4903 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4908 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014),
4966 x86_pmu.pebs_broken = 1; in intel_snb_check_microcode()
5114 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5115 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5244 if (val > 1) in freeze_on_smi_store()
5255 on_each_cpu(flip_smm_bit, &val, 1); in freeze_on_smi_store()
5300 on_each_cpu(update_tfa_sched, NULL, 1); in set_sysctl_tfa()
5473 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hy…
5474 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hy…
5533 return (cpu >= nr_cpu_ids) ? -1 : cpu; in hybrid_find_supported_cpu()
5619 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", in intel_pmu_check_num_counters()
5623 *intel_ctrl = (1ULL << *num_counters) - 1; in intel_pmu_check_num_counters()
5626 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", in intel_pmu_check_num_counters()
5639 struct event_constraint *c; in intel_pmu_check_event_constraints() local
5648 for_each_event_constraint(c, event_constraints) { in intel_pmu_check_event_constraints()
5653 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { in intel_pmu_check_event_constraints()
5659 c->idxmsk64 = 0; in intel_pmu_check_event_constraints()
5660 c->weight = hweight64(c->idxmsk64); in intel_pmu_check_event_constraints()
5664 if (c->cmask == FIXED_EVENT_FLAGS) { in intel_pmu_check_event_constraints()
5666 c->idxmsk64 &= intel_ctrl; in intel_pmu_check_event_constraints()
5672 if (!use_fixed_pseudo_encoding(c->code)) in intel_pmu_check_event_constraints()
5673 c->idxmsk64 |= (1ULL << num_counters) - 1; in intel_pmu_check_event_constraints()
5675 c->idxmsk64 &= in intel_pmu_check_event_constraints()
5677 c->weight = hweight64(c->idxmsk64); in intel_pmu_check_event_constraints()
5715 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; in intel_pmu_check_hybrid_pmus()
5776 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
5788 if (version > 1 && version < 5) { in intel_pmu_init()
5794 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; in intel_pmu_init()
5870 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5871 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ in intel_pmu_init()
5873 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5877 x86_pmu.pebs_no_tlb = 1; in intel_pmu_init()
5987 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6014 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6058 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6059 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ in intel_pmu_init()
6061 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6096 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ in intel_pmu_init()
6098 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6099 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ in intel_pmu_init()
6101 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6115 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
6137 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ in intel_pmu_init()
6139 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6191 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
6193 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
6195 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6197 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6258 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ in intel_pmu_init()
6260 "event=0xd,umask=0x1,cmask=1"; in intel_pmu_init()
6262 "event=0xd,umask=0x1,cmask=1,any=1"; in intel_pmu_init()
6302 x86_pmu.pebs_ept = 1; in intel_pmu_init()
6313 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6442 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; in intel_pmu_init()
6462 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, in intel_pmu_init()
6465 pmu->intel_cap.perf_metrics = 1; in intel_pmu_init()
6483 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, in intel_pmu_init()
6487 pmu->intel_cap.pebs_output_pt_available = 1; in intel_pmu_init()
6491 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6501 case 1: in intel_pmu_init()
6526 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; in intel_pmu_init()
6600 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
6606 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; in intel_pmu_init()
6624 int c; in fixup_ht_bug() local
6631 if (topology_max_smt_threads() > 1) { in fixup_ht_bug()
6648 for_each_online_cpu(c) in fixup_ht_bug()
6649 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); in fixup_ht_bug()