83 struct perf_ibs {  struct
180 static struct perf_ibs perf_ibs_fetch;
181 static struct perf_ibs perf_ibs_op;
183 static struct perf_ibs *get_ibs_pmu(int type)  in get_ibs_pmu()
249 	struct perf_ibs *perf_ibs;  in perf_ibs_init()  local
253 	perf_ibs = get_ibs_pmu(event->attr.type);  in perf_ibs_init()
254 	if (perf_ibs) {  in perf_ibs_init()
257 		perf_ibs = &perf_ibs_op;  in perf_ibs_init()
263 	if (event->pmu != &perf_ibs->pmu)  in perf_ibs_init()
266 	if (config & ~perf_ibs->config_mask)  in perf_ibs_init()
270 		if (config & perf_ibs->cnt_mask)  in perf_ibs_init()
284 		max_cnt = config & perf_ibs->cnt_mask;  in perf_ibs_init()
285 		config &= ~perf_ibs->cnt_mask;  in perf_ibs_init()
300 	hwc->config_base = perf_ibs->msr;  in perf_ibs_init()
306 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,  in perf_ibs_set_period()  argument
312 	overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);  in perf_ibs_set_period()
347 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,  in perf_ibs_event_update()  argument
350 	u64 count = perf_ibs->get_count(*config);  in perf_ibs_event_update()
359 		count = perf_ibs->get_count(*config);  in perf_ibs_event_update()
363 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,  in perf_ibs_enable_event()  argument
368 	if (perf_ibs->fetch_count_reset_broken)  in perf_ibs_enable_event()
369 		wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);  in perf_ibs_enable_event()
371 	wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);  in perf_ibs_enable_event()
381 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,  in perf_ibs_disable_event()  argument
384 	config &= ~perf_ibs->cnt_mask;  in perf_ibs_disable_event()
387 	config &= ~perf_ibs->enable_mask;  in perf_ibs_disable_event()
400 	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);  in perf_ibs_start()  local
401 	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);  in perf_ibs_start()
410 	perf_ibs_set_period(perf_ibs, hwc, &period);  in perf_ibs_start()
411 	if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {  in perf_ibs_start()
423 	perf_ibs_enable_event(perf_ibs, hwc, config);  in perf_ibs_start()
431 	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);  in perf_ibs_stop()  local
432 	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);  in perf_ibs_stop()
454 		perf_ibs_disable_event(perf_ibs, hwc, config);  in perf_ibs_stop()
476 	config &= ~perf_ibs->valid_mask;  in perf_ibs_stop()
478 	perf_ibs_event_update(perf_ibs, event, &config);  in perf_ibs_stop()
484 	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);  in perf_ibs_add()  local
485 	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);  in perf_ibs_add()
502 	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);  in perf_ibs_del()  local
503 	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);  in perf_ibs_del()
632 static struct perf_ibs perf_ibs_fetch = {
656 static struct perf_ibs perf_ibs_op = {
999 static int perf_ibs_get_offset_max(struct perf_ibs *perf_ibs, u64 sample_type,  in perf_ibs_get_offset_max()  argument
1003 	    (perf_ibs == &perf_ibs_op &&  in perf_ibs_get_offset_max()
1008 		return perf_ibs->offset_max;  in perf_ibs_get_offset_max()
1014 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)  in perf_ibs_handle_irq()  argument
1016 	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);  in perf_ibs_handle_irq()
1048 	if (!(*buf++ & perf_ibs->valid_mask))  in perf_ibs_handle_irq()
1052 	perf_ibs_event_update(perf_ibs, event, config);  in perf_ibs_handle_irq()
1054 	if (!perf_ibs_set_period(perf_ibs, hwc, &period))  in perf_ibs_handle_irq()
1060 	check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));  in perf_ibs_handle_irq()
1062 	offset_max = perf_ibs_get_offset_max(perf_ibs, event->attr.sample_type, check_rip);  in perf_ibs_handle_irq()
1067 		offset = find_next_bit(perf_ibs->offset_mask,  in perf_ibs_handle_irq()
1068 				       perf_ibs->offset_max,  in perf_ibs_handle_irq()
1077 		if (perf_ibs == &perf_ibs_op) {  in perf_ibs_handle_irq()
1087 		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {  in perf_ibs_handle_irq()
1099 		if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))  in perf_ibs_handle_irq()
1117 	if (perf_ibs == &perf_ibs_op)  in perf_ibs_handle_irq()
1135 		if (perf_ibs == &perf_ibs_op) {  in perf_ibs_handle_irq()
1145 		perf_ibs_enable_event(perf_ibs, hwc, new_config);  in perf_ibs_handle_irq()
1171 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)  in perf_ibs_pmu_init()  argument
1180 	perf_ibs->pcpu = pcpu;  in perf_ibs_pmu_init()
1182 	ret = perf_pmu_register(&perf_ibs->pmu, name, -1);  in perf_ibs_pmu_init()
1184 		perf_ibs->pcpu = NULL;  in perf_ibs_pmu_init()