21 static u32 ibs_caps;  variable
337 		if (ibs_caps & IBS_CAPS_OPCNTEXT)  in get_ibs_op_count()
339 	} else if (ibs_caps & IBS_CAPS_RDWROPCNT) {  in get_ibs_op_count()
411 	if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {  in perf_ibs_start()
550 	return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0;  in zen4_ibs_extensions_is_visible()
600 	return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0;  in cnt_ctl_is_visible()
700 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_data_src()
748 	if (ibs_caps & IBS_CAPS_ZEN4) {  in perf_ibs_get_mem_lvl()
762 	if (ibs_caps & IBS_CAPS_ZEN4 &&  in perf_ibs_get_mem_lvl()
769 	if (ibs_caps & IBS_CAPS_ZEN4) {  in perf_ibs_get_mem_lvl()
791 	if (ibs_caps & IBS_CAPS_ZEN4 && ibs_data_src == IBS_DATA_SRC_EXT_PMEM) {  in perf_ibs_get_mem_lvl()
802 	if (ibs_caps & IBS_CAPS_ZEN4 &&  in perf_ibs_get_mem_lvl()
877 	if (ibs_caps & IBS_CAPS_ZEN4) {  in perf_ibs_get_mem_snoop()
1057 	ibs_data.caps = ibs_caps;  in perf_ibs_handle_irq()
1060 	check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));  in perf_ibs_handle_irq()
1078 			if (ibs_caps & IBS_CAPS_BRNTRGT) {  in perf_ibs_handle_irq()
1082 			if (ibs_caps & IBS_CAPS_OPDATA4) {  in perf_ibs_handle_irq()
1087 		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {  in perf_ibs_handle_irq()
1136 			if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_ibs_handle_irq()
1140 			if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))  in perf_ibs_handle_irq()
1203 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_fetch_init()
1214 	if (ibs_caps & IBS_CAPS_OPCNT)  in perf_ibs_op_init()
1217 	if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_ibs_op_init()
1223 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_op_init()
1248 	pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);  in perf_event_ibs_init()
1297 	return ibs_caps;  in get_ibs_caps()
1526 	ibs_caps = caps;  in amd_ibs_init()