Lines Matching +full:0 +full:x48
54 /* When an irrecoverable trap occurs at tl > 0, the trap entry
73 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, " in dump_tl1_traplog()
77 for (i = 0; i < limit; i++) { in dump_tl1_traplog()
93 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap()
96 if (lvl < 0x100) { in bad_trap()
101 lvl -= 0x100; in bad_trap()
107 regs->tpc &= 0xffffffff; in bad_trap()
108 regs->tnpc &= 0xffffffff; in bad_trap()
119 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap_tl1()
124 sprintf (buffer, "Bad trap %lx at tl>0", lvl); in bad_trap_tl1()
152 ret = 0; in sprintf_dimm()
163 int ret = 0; in register_dimm_printer()
192 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception()
201 regs->tpc &= 0xffffffff; in spitfire_insn_access_exception()
202 regs->tnpc &= 0xffffffff; in spitfire_insn_access_exception()
212 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception_tl1()
222 unsigned short ctx = (type_ctx & 0xffff); in sun4v_insn_access_exception()
225 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception()
236 regs->tpc &= 0xffffffff; in sun4v_insn_access_exception()
237 regs->tnpc &= 0xffffffff; in sun4v_insn_access_exception()
245 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception_tl1()
272 if ((insn & 0xc0800000) == 0xc0800000) { /* op=3, op3[4]=1 */ in is_no_fault_exception()
273 if (insn & 0x2000) /* immediate offset */ in is_no_fault_exception()
277 if ((asi & 0xf6) == ASI_PNF) { in is_no_fault_exception()
278 if (insn & 0x200000) /* op3[2], stores */ in is_no_fault_exception()
280 if (insn & 0x1000000) /* op3[5:4]=3 (fp) */ in is_no_fault_exception()
295 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception()
331 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception_tl1()
341 unsigned short ctx = (type_ctx & 0xffff); in sun4v_data_access_exception()
344 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception()
370 regs->tpc &= 0xffffffff; in sun4v_data_access_exception()
371 regs->tnpc &= 0xffffffff; in sun4v_data_access_exception()
376 /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV in sun4v_data_access_exception()
401 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception_tl1()
421 for (va = 0; va < (PAGE_SIZE << 1); va += 32) { in spitfire_clean_and_reenable_l1_caches()
422 spitfire_put_icache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
423 spitfire_put_dcache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
429 "stxa %0, [%%g0] %1\n\t" in spitfire_clean_and_reenable_l1_caches()
440 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in spitfire_enable_estate_errors()
448 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
449 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
450 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
451 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
452 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
453 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
454 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
455 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
456 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
457 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
458 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
459 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
460 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
461 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
462 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
463 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
464 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
465 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
466 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
467 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
468 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
469 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
470 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
471 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
472 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
473 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
474 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
475 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
476 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
477 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
478 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
479 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
490 scode = ecc_syndrome_table[udbl & 0xff]; in spitfire_log_udb_syndrome()
491 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
501 scode = ecc_syndrome_table[udbh & 0xff]; in spitfire_log_udb_syndrome()
502 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
526 0, TRAP_TYPE_CEE, SIGTRAP); in spitfire_cee_log()
550 0, tt, SIGTRAP); in spitfire_ue_log()
567 regs->tpc &= 0xffffffff; in spitfire_ue_log()
568 regs->tnpc &= 0xffffffff; in spitfire_ue_log()
570 force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0); in spitfire_ue_log()
580 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0; in spitfire_access_error()
606 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
610 "r" (0x0), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
614 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
618 "r" (0x18), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
635 __asm__ __volatile__("ldxa [%%g0] %1, %0" in cheetah_enable_pcache()
639 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_enable_pcache()
718 { 0, NULL },
759 { 0, NULL },
818 { 0, NULL },
834 if ((afsr & CHAFSR_TL1) != 0UL) in cheetah_get_error_log()
861 largest_size = 0UL; in cheetah_ecache_flush_init()
862 smallest_linesize = ~0UL; in cheetah_ecache_flush_init()
864 for (i = 0; i < NR_CPUS; i++) { in cheetah_ecache_flush_init()
880 if (largest_size == 0UL || smallest_linesize == ~0UL) { in cheetah_ecache_flush_init()
891 if (ecache_flush_physbase == ~0UL) { in cheetah_ecache_flush_init()
900 for (order = 0; order < MAX_ORDER; order++) { in cheetah_ecache_flush_init()
911 memset(cheetah_error_log, 0, PAGE_SIZE << order); in cheetah_ecache_flush_init()
916 for (i = 0; i < 2 * NR_CPUS; i++) in cheetah_ecache_flush_init()
919 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); in cheetah_ecache_flush_init()
922 cheetah_error_table = &__jalapeno_error_table[0]; in cheetah_ecache_flush_init()
924 } else if ((ver >> 32) == 0x003e0015) { in cheetah_ecache_flush_init()
925 cheetah_error_table = &__cheetah_plus_error_table[0]; in cheetah_ecache_flush_init()
928 cheetah_error_table = &__cheetah_error_table[0]; in cheetah_ecache_flush_init()
956 __asm__ __volatile__("1: subcc %0, %4, %0\n\t" in cheetah_flush_ecache()
958 " ldxa [%2 + %0] %3, %%g0\n\t" in cheetah_flush_ecache()
960 : "0" (flush_size), "r" (flush_base), in cheetah_flush_ecache()
972 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t" in cheetah_flush_ecache_line()
994 for (addr = 0; addr < icache_size; addr += icache_line_size) { in __cheetah_flush_icache()
995 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in __cheetah_flush_icache()
1008 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_flush_icache()
1009 "or %0, %2, %%g1\n\t" in cheetah_flush_icache()
1019 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_flush_icache()
1033 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_flush_dcache()
1034 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in cheetah_flush_dcache()
1054 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_plus_zap_dcache_parity()
1059 "stxa %0, [%1] %2\n\t" in cheetah_plus_zap_dcache_parity()
1066 "stxa %%g0, [%0] %1\n\t" in cheetah_plus_zap_dcache_parity()
1103 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1110 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1111 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1112 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1113 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1114 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1115 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1147 unsigned long tmp = 0; in cheetah_get_hipri()
1150 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_hipri()
1151 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL) in cheetah_get_hipri()
1161 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_string()
1162 if ((bit & cheetah_error_table[i].mask) != 0UL) in cheetah_get_string()
1177 (afsr & CHAFSR_TL1) ? 1 : 0); in cheetah_log_errors()
1236 info->dcache_data[0], in cheetah_log_errors()
1251 info->icache_data[0], in cheetah_log_errors()
1266 info->ecache_data[0], in cheetah_log_errors()
1272 while (afsr != 0UL) { in cheetah_log_errors()
1289 int ret = 0; in cheetah_recheck_errors()
1291 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1294 if ((afsr & cheetah_afsr_errors) != 0) { in cheetah_recheck_errors()
1296 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1304 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_recheck_errors()
1347 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1349 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1357 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1359 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1371 recoverable = 0; in cheetah_fecc_handler()
1384 recoverable = 0; in cheetah_fecc_handler()
1408 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t" in cheetah_fix_ce()
1409 "andn %0, %1, %%g1\n\t" in cheetah_fix_ce()
1428 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1431 "ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1441 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t" in cheetah_fix_ce()
1450 ret = 0; in cheetah_fix_ce()
1454 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_fix_ce()
1467 return 0; in cheetah_check_main_memory()
1503 if (is_memory && (afsr & CHAFSR_CE) != 0UL) { in cheetah_cee_handler()
1513 flush_all = flush_line = 0; in cheetah_cee_handler()
1514 if ((afsr & CHAFSR_EDC) != 0UL) { in cheetah_cee_handler()
1519 } else if ((afsr & CHAFSR_CPC) != 0UL) { in cheetah_cee_handler()
1530 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1532 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1546 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1548 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1560 recoverable = 0; in cheetah_cee_handler()
1584 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1586 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1594 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1596 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1641 flush_all = flush_line = 0; in cheetah_deferred_handler()
1642 if ((afsr & CHAFSR_EDU) != 0UL) { in cheetah_deferred_handler()
1647 } else if ((afsr & CHAFSR_BERR) != 0UL) { in cheetah_deferred_handler()
1658 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1660 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1674 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1676 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1688 recoverable = 0; in cheetah_deferred_handler()
1701 recoverable = 0; in cheetah_deferred_handler()
1720 if ((regs->tstate & TSTATE_PRIV) == 0UL) { in cheetah_deferred_handler()
1733 recoverable = 0; in cheetah_deferred_handler()
1740 recoverable = 0; in cheetah_deferred_handler()
1752 recoverable = 0; in cheetah_deferred_handler()
1761 * Bit0: 0=dcache,1=icache
1762 * Bit1: 0=recoverable,1=unrecoverable
1769 if (type & 0x1) in cheetah_plus_parity_error()
1776 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_plus_parity_error()
1778 "stxa %%g1, [%%g0] %0\n\t" in cheetah_plus_parity_error()
1785 if (type & 0x2) { in cheetah_plus_parity_error()
1788 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1796 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1803 /*0x00*/u64 err_handle;
1806 /*0x08*/u64 err_stick;
1808 /*0x10*/u8 reserved_1[3];
1811 /*0x13*/u8 err_type;
1812 #define SUN4V_ERR_TYPE_UNDEFINED 0
1822 /*0x14*/u32 err_attrs;
1823 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1824 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1825 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1826 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1827 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1828 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1829 #define SUN4V_ERR_ATTRS_ASR 0x00000040
1830 #define SUN4V_ERR_ATTRS_ASI 0x00000080
1831 #define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1832 #define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1833 #define SUN4V_ERR_ATTRS_MCD 0x00000800
1835 #define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1837 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1839 #define SUN4V_ERR_SPSTATE_FAULTED 0
1847 /*0x18*/u64 err_raddr;
1850 /*0x20*/u32 err_size;
1853 /*0x24*/u16 err_cpu;
1856 /*0x26*/u16 err_secs;
1859 /*0x28*/u8 err_asi;
1861 /*0x29*/u8 reserved_2;
1864 /*0x2a*/u16 err_asr;
1865 #define SUN4V_ERR_ASR_VALID 0x8000
1867 /*0x2c*/u32 reserved_3;
1868 /*0x30*/u64 reserved_4;
1869 /*0x38*/u64 reserved_5;
1872 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1873 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1921 for (i = 0; i < ARRAY_SIZE(attr_names); i++) { in sun4v_emit_err_attr_strings()
1958 addr = compute_effective_address(regs, insn, 0); in sun4v_report_real_raddr()
1960 printk("%s: insn effective address [0x%016llx]\n", in sun4v_report_real_raddr()
1972 printk("%s: TPC [0x%016lx] <%pS>\n", in sun4v_log_error()
1976 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]); in sun4v_log_error()
1980 printk("%s: handle [0x%016llx] stick [0x%016llx]\n", in sun4v_log_error()
1986 printk("%s: attrs [0x%08x] < ", pfx, attrs); in sun4v_log_error()
1996 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr); in sun4v_log_error()
1998 if (ent->err_raddr == ~(u64)0) in sun4v_log_error()
2003 printk("%s: size [0x%x]\n", pfx, ent->err_size); in sun4v_log_error()
2012 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi); in sun4v_log_error()
2017 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0) in sun4v_log_error()
2018 printk("%s: reg [0x%04x]\n", in sun4v_log_error()
2023 if ((cnt = atomic_read(ocnt)) != 0) { in sun4v_log_error()
2024 atomic_set(ocnt, 0); in sun4v_log_error()
2036 if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34, in do_mcd_err()
2094 ent->err_handle = 0; in sun4v_resum_error()
2144 (insn >> 25) & 0x1f); in sun4v_get_vaddr()
2146 return 0; in sun4v_get_vaddr()
2160 if (addr == ~(u64)0) { in sun4v_nonresum_error_user_handled()
2173 while (page_cnt-- > 0) { in sun4v_nonresum_error_user_handled()
2212 ent->err_handle = 0; in sun4v_nonresum_error()
2321 unsigned long fsr = current_thread_info()->xfsr[0]; in do_fpe_common()
2325 regs->tpc &= 0xffffffff; in do_fpe_common()
2326 regs->tnpc &= 0xffffffff; in do_fpe_common()
2329 if ((fsr & 0x1c000) == (1 << 14)) { in do_fpe_common()
2330 if (fsr & 0x10) in do_fpe_common()
2332 else if (fsr & 0x08) in do_fpe_common()
2334 else if (fsr & 0x04) in do_fpe_common()
2336 else if (fsr & 0x02) in do_fpe_common()
2338 else if (fsr & 0x01) in do_fpe_common()
2350 0, 0x24, SIGFPE) == NOTIFY_STOP) in do_fpieee()
2362 int ret = 0; in do_fpother()
2365 0, 0x25, SIGFPE) == NOTIFY_STOP) in do_fpother()
2368 switch ((current_thread_info()->xfsr[0] & 0x1c000)) { in do_fpother()
2386 0, 0x26, SIGEMT) == NOTIFY_STOP) in do_tof()
2392 regs->tpc &= 0xffffffff; in do_tof()
2393 regs->tnpc &= 0xffffffff; in do_tof()
2405 0, 0x28, SIGFPE) == NOTIFY_STOP) in do_div0()
2411 regs->tpc &= 0xffffffff; in do_div0()
2412 regs->tnpc &= 0xffffffff; in do_div0()
2444 for (i = 0; i < 9; i++) in user_instruction_dump()
2453 int count = 0; in show_stack()
2455 int graph = 0; in show_stack()
2462 if (ksp == 0UL) { in show_stack()
2464 asm("mov %%fp, %0" : "=r" (ksp)); in show_stack()
2522 int count = 0; in die_if_kernel()
2532 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV); in die_if_kernel()
2555 regs->tpc &= 0xffffffff; in die_if_kernel()
2556 regs->tnpc &= 0xffffffff; in die_if_kernel()
2566 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2567 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2577 0, 0x10, SIGILL) == NOTIFY_STOP) in do_illegal_instruction()
2585 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ { in do_illegal_instruction()
2588 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ { in do_illegal_instruction()
2618 0, 0x34, SIGSEGV) == NOTIFY_STOP) in mem_address_unaligned()
2636 0, 0x34, SIGSEGV) == NOTIFY_STOP) in sun4v_do_mna()
2660 0, 0x8, SIGSEGV) == NOTIFY_STOP) in sun4v_mem_corrupt_detect_precise()
2690 regs->tpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2691 regs->tnpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2701 0, 0x11, SIGILL) == NOTIFY_STOP) in do_privop()
2705 regs->tpc &= 0xffffffff; in do_privop()
2706 regs->tnpc &= 0xffffffff; in do_privop()
2813 regs->tpc &= 0xffffffff; in do_getpsr()
2814 regs->tnpc &= 0xffffffff; in do_getpsr()
2818 u64 cpu_mondo_counter[NR_CPUS] = {0};
2831 p->pgd_paddr = 0; in init_cur_cpu_trap()