Lines Matching +full:0 +full:xffe40000
32 DEFINE_RES_MEM(0xffe40000, 0x100),
33 DEFINE_RES_IRQ(evt2irq(0x8c0)),
38 .id = 0,
53 DEFINE_RES_MEM(0xffe41000, 0x100),
54 DEFINE_RES_IRQ(evt2irq(0x8e0)),
74 DEFINE_RES_MEM(0xffe42000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x900)),
95 DEFINE_RES_MEM(0xffe43000, 0x100),
96 DEFINE_RES_IRQ(evt2irq(0x920)),
116 DEFINE_RES_MEM(0xffe44000, 0x100),
117 DEFINE_RES_IRQ(evt2irq(0x940)),
137 DEFINE_RES_MEM(0xffe43000, 0x100),
138 DEFINE_RES_IRQ(evt2irq(0x960)),
153 [0] = {
155 .start = 0xFFFC5000,
156 .end = 0xFFFC5000 + 0x26 - 1,
160 .start = evt2irq(0xC00),
172 /* I2C 0 */
174 [0] = {
176 .start = 0xFFC70000,
177 .end = 0xFFC7000A - 1,
181 .start = evt2irq(0x860),
188 .id = 0,
199 DEFINE_RES_MEM(0xffd80000, 0x30),
200 DEFINE_RES_IRQ(evt2irq(0x400)),
201 DEFINE_RES_IRQ(evt2irq(0x420)),
202 DEFINE_RES_IRQ(evt2irq(0x440)),
207 .id = 0,
220 DEFINE_RES_MEM(0xffd81000, 0x30),
221 DEFINE_RES_IRQ(evt2irq(0x480)),
222 DEFINE_RES_IRQ(evt2irq(0x4a0)),
223 DEFINE_RES_IRQ(evt2irq(0x4c0)),
241 DEFINE_RES_MEM(0xffd82000, 0x30),
242 DEFINE_RES_IRQ(evt2irq(0x500)),
243 DEFINE_RES_IRQ(evt2irq(0x520)),
244 DEFINE_RES_IRQ(evt2irq(0x540)),
288 #define GROUP 0
290 UNUSED = 0,
368 INTC_VECT(DU, 0x3E0),
369 INTC_VECT(TMU00, 0x400),
370 INTC_VECT(TMU10, 0x420),
371 INTC_VECT(TMU20, 0x440),
372 INTC_VECT(TMU30, 0x480),
373 INTC_VECT(TMU40, 0x4A0),
374 INTC_VECT(TMU50, 0x4C0),
375 INTC_VECT(TMU51, 0x4E0),
376 INTC_VECT(TMU60, 0x500),
377 INTC_VECT(TMU70, 0x520),
378 INTC_VECT(TMU80, 0x540),
379 INTC_VECT(RESET_WDT, 0x560),
380 INTC_VECT(USB, 0x580),
381 INTC_VECT(HUDI, 0x600),
382 INTC_VECT(SHDMAC, 0x620),
383 INTC_VECT(SSI0, 0x6C0),
384 INTC_VECT(SSI1, 0x6E0),
385 INTC_VECT(SSI2, 0x700),
386 INTC_VECT(SSI3, 0x720),
387 INTC_VECT(VIN0, 0x740),
388 INTC_VECT(RGPVG, 0x760),
389 INTC_VECT(_2DG, 0x780),
390 INTC_VECT(MMC, 0x7A0),
391 INTC_VECT(HSPI, 0x7E0),
392 INTC_VECT(LBSCATA, 0x840),
393 INTC_VECT(I2C0, 0x860),
394 INTC_VECT(RCAN0, 0x880),
395 INTC_VECT(SCIF0, 0x8A0),
396 INTC_VECT(SCIF1, 0x8C0),
397 INTC_VECT(SCIF2, 0x900),
398 INTC_VECT(SCIF3, 0x920),
399 INTC_VECT(SCIF4, 0x940),
400 INTC_VECT(SCIF5, 0x960),
401 INTC_VECT(LBSCDMAC0, 0x9E0),
402 INTC_VECT(LBSCDMAC1, 0xA00),
403 INTC_VECT(LBSCDMAC2, 0xA20),
404 INTC_VECT(RCAN1, 0xA60),
405 INTC_VECT(SDHI0, 0xAE0),
406 INTC_VECT(SDHI1, 0xB00),
407 INTC_VECT(IEBUS, 0xB20),
408 INTC_VECT(HPBDMAC0_3, 0xB60),
409 INTC_VECT(HPBDMAC4_10, 0xB80),
410 INTC_VECT(HPBDMAC11_18, 0xBA0),
411 INTC_VECT(HPBDMAC19_22, 0xBC0),
412 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
413 INTC_VECT(RTC, 0xC00),
414 INTC_VECT(VIN1, 0xC20),
415 INTC_VECT(LCDC, 0xC40),
416 INTC_VECT(SRC0, 0xC60),
417 INTC_VECT(SRC1, 0xC80),
418 INTC_VECT(GETHER, 0xCA0),
419 INTC_VECT(SDHI2, 0xCC0),
420 INTC_VECT(GPIO0_3, 0xCE0),
421 INTC_VECT(GPIO4_5, 0xD00),
422 INTC_VECT(STIF0, 0xD20),
423 INTC_VECT(STIF1, 0xD40),
424 INTC_VECT(ADMAC, 0xDA0),
425 INTC_VECT(HIF, 0xDC0),
426 INTC_VECT(FLCTL, 0xDE0),
427 INTC_VECT(ADC, 0xE00),
428 INTC_VECT(MTU2, 0xE20),
429 INTC_VECT(RSPI, 0xE40),
430 INTC_VECT(QSPI, 0xE60),
431 INTC_VECT(HSCIF, 0xFC0),
432 INTC_VECT(VEU3F_VE3, 0xF40),
464 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
465 { 0,
467 SDHI, /* SDHI 0-2 */
474 STIF_M, /* STIF 0,1 */
475 GPIO_M, /* GPIO 0-5*/
477 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
478 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
480 SRC_M, /* SRC 0,1 */
482 SCIF_M, /* SCIF 0-5, HSCIF */
487 SSI, /* SSI 0-3 */
493 I2C0, /* I2C */ /* I2C 0, 1*/
500 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
502 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
504 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
506 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
508 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
510 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
512 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
514 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
516 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
517 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
518 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
520 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
522 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
532 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
533 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
537 { 0xFF80201C, 32, 2, /* ICR1 */
542 { 0xFF802024, 0, 32, /* INTREQ */
547 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
552 { 0xFF802010, 0, 32, 4, /* INTPRI */
564 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
565 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
566 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
567 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
568 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
569 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
570 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
571 INTC_VECT(IRL0_HHHL, 0x3c0),
577 #define INTC_ICR0 0xFF802000
578 #define INTC_INTMSK0 0xFF802044
579 #define INTC_INTMSK1 0xFF802048
580 #define INTC_INTMSKCLR0 0xFF802064
581 #define INTC_INTMSKCLR1 0xFF802068
585 /* disable IRQ3-0 */ in plat_irq_setup()
586 __raw_writel(0xF0000000, INTC_INTMSK0); in plat_irq_setup()
588 /* disable IRL3-0 */ in plat_irq_setup()
589 __raw_writel(0x80000000, INTC_INTMSK1); in plat_irq_setup()
591 /* select IRL mode for IRL3-0 */ in plat_irq_setup()
592 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); in plat_irq_setup()
595 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
604 /* select IRQ mode for IRL3-0 */ in plat_irq_setup_pins()
605 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
610 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
611 __raw_writel(0xf0000000, INTC_INTMSKCLR0); in plat_irq_setup_pins()
615 __raw_writel(0x80000000, INTC_INTMSKCLR0); in plat_irq_setup_pins()