Lines Matching +full:parallel +full:- +full:memories
1 // SPDX-License-Identifier: GPL-2.0
3 * Performance events support for SH-4A performance counters
24 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
59 * ---------- -----------
65 * 0x0203 instruction execution in parallel
72 * 0x0028 number of accesses to instruction memories
76 * 0x0030 number of reads to operand memories
77 * 0x0038 number of writes to operand memories
102 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
103 [PERF_COUNT_HW_CACHE_MISSES] = 0x002a, /* I-cache */
105 [PERF_COUNT_HW_BRANCH_MISSES] = -1,
106 [PERF_COUNT_HW_BUS_CYCLES] = -1,
137 [ C(RESULT_ACCESS) ] = -1,
138 [ C(RESULT_MISS) ] = -1,
182 [ C(RESULT_ACCESS) ] = -1,
183 [ C(RESULT_MISS) ] = -1,
186 [ C(RESULT_ACCESS) ] = -1,
187 [ C(RESULT_MISS) ] = -1,
193 [ C(RESULT_ACCESS) ] = -1,
194 [ C(RESULT_MISS) ] = -1,
197 [ C(RESULT_ACCESS) ] = -1,
198 [ C(RESULT_MISS) ] = -1,
201 [ C(RESULT_ACCESS) ] = -1,
202 [ C(RESULT_MISS) ] = -1,
208 [ C(RESULT_ACCESS) ] = -1,
209 [ C(RESULT_MISS) ] = -1,
212 [ C(RESULT_ACCESS) ] = -1,
213 [ C(RESULT_MISS) ] = -1,
216 [ C(RESULT_ACCESS) ] = -1,
217 [ C(RESULT_MISS) ] = -1,
251 tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE; in sh4a_pmu_enable()
294 return -ENODEV; in sh4a_pmu_init()