Lines Matching +full:1 +full:c
5 * Copyright (C) 2009, 2010 Paul Mundt
18 #define CCBR_DUC (1 << 3)
19 #define CCBR_CMDS (1 << 1)
20 #define CCBR_PPCE (1 << 0)
42 #define PMCAT_OVF3 (1 << 27)
43 #define PMCAT_CNN3 (1 << 26)
44 #define PMCAT_CLR3 (1 << 25)
45 #define PMCAT_OVF2 (1 << 19)
46 #define PMCAT_CLR2 (1 << 17)
47 #define PMCAT_OVF1 (1 << 11)
48 #define PMCAT_CNN1 (1 << 10)
49 #define PMCAT_CLR1 (1 << 9)
50 #define PMCAT_OVF0 (1 << 3)
51 #define PMCAT_CLR0 (1 << 1)
97 #define PMCAT_EMU_CLR_MASK ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
105 [PERF_COUNT_HW_BRANCH_MISSES] = -1,
106 [PERF_COUNT_HW_BUS_CYCLES] = -1,
109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
127 [ C(RESULT_MISS) ] = 0,
131 [ C(L1I) ] = {
132 [ C(OP_READ) ] = {
133 [ C(RESULT_ACCESS) ] = 0x0029,
134 [ C(RESULT_MISS) ] = 0x002a,
136 [ C(OP_WRITE) ] = {
137 [ C(RESULT_ACCESS) ] = -1,
138 [ C(RESULT_MISS) ] = -1,
140 [ C(OP_PREFETCH) ] = {
141 [ C(RESULT_ACCESS) ] = 0,
142 [ C(RESULT_MISS) ] = 0,
146 [ C(LL) ] = {
147 [ C(OP_READ) ] = {
148 [ C(RESULT_ACCESS) ] = 0x0030,
149 [ C(RESULT_MISS) ] = 0,
151 [ C(OP_WRITE) ] = {
152 [ C(RESULT_ACCESS) ] = 0x0038,
153 [ C(RESULT_MISS) ] = 0,
155 [ C(OP_PREFETCH) ] = {
156 [ C(RESULT_ACCESS) ] = 0,
157 [ C(RESULT_MISS) ] = 0,
161 [ C(DTLB) ] = {
162 [ C(OP_READ) ] = {
163 [ C(RESULT_ACCESS) ] = 0x0222,
164 [ C(RESULT_MISS) ] = 0x0220,
166 [ C(OP_WRITE) ] = {
167 [ C(RESULT_ACCESS) ] = 0,
168 [ C(RESULT_MISS) ] = 0,
170 [ C(OP_PREFETCH) ] = {
171 [ C(RESULT_ACCESS) ] = 0,
172 [ C(RESULT_MISS) ] = 0,
176 [ C(ITLB) ] = {
177 [ C(OP_READ) ] = {
178 [ C(RESULT_ACCESS) ] = 0,
179 [ C(RESULT_MISS) ] = 0x02a0,
181 [ C(OP_WRITE) ] = {
182 [ C(RESULT_ACCESS) ] = -1,
183 [ C(RESULT_MISS) ] = -1,
185 [ C(OP_PREFETCH) ] = {
186 [ C(RESULT_ACCESS) ] = -1,
187 [ C(RESULT_MISS) ] = -1,
191 [ C(BPU) ] = {
192 [ C(OP_READ) ] = {
193 [ C(RESULT_ACCESS) ] = -1,
194 [ C(RESULT_MISS) ] = -1,
196 [ C(OP_WRITE) ] = {
197 [ C(RESULT_ACCESS) ] = -1,
198 [ C(RESULT_MISS) ] = -1,
200 [ C(OP_PREFETCH) ] = {
201 [ C(RESULT_ACCESS) ] = -1,
202 [ C(RESULT_MISS) ] = -1,
206 [ C(NODE) ] = {
207 [ C(OP_READ) ] = {
208 [ C(RESULT_ACCESS) ] = -1,
209 [ C(RESULT_MISS) ] = -1,
211 [ C(OP_WRITE) ] = {
212 [ C(RESULT_ACCESS) ] = -1,
213 [ C(RESULT_MISS) ] = -1,
215 [ C(OP_PREFETCH) ] = {
216 [ C(RESULT_ACCESS) ] = -1,
217 [ C(RESULT_MISS) ] = -1,