Lines Matching +full:down +full:- +full:scaling

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
5  * Additional SH4-202 support for the clock framework
25 	return clk->parent->rate / frqcr3_divisors[idx];  in emi_clk_recalc()
30 	int divisor = clk->parent->rate / rate;  in frqcr3_lookup()
53 	return clk->parent->rate / frqcr3_divisors[idx];  in femi_clk_recalc()
72 	 * range for instance). We deal with this by scaling it back down  in shoc_clk_init()
75 	 * Start scaling from the high end down until we find something  in shoc_clk_init()
81 		if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)  in shoc_clk_init()
91 	return clk->parent->rate / frqcr3_divisors[idx];  in shoc_clk_recalc()
116 		return -EINVAL;  in shoc_clk_set_rate()
125 	clk->rate = clk->parent->rate / frqcr3_divisors[tmp];  in shoc_clk_set_rate()
165 		clkp->parent = clk;  in arch_clk_init()