Lines Matching +full:d +full:- +full:tlb +full:- +full:sets

1 // SPDX-License-Identifier: GPL-2.0
7  * Copyright (C) 2002 - 2009  Paul Mundt
39  * Generic wrapper for command line arguments to disable on-chip
85 	 * Disable support for slottable sleep instruction, non-nop  in expmask_init()
87 	 * the memory-mapped cache array.  in expmask_init()
98 /* 2nd-level cache init */
104  * Generic first-level cache init
115 	 * At this point we don't know whether the cache is enabled or not - a  in cache_init()
120 	 * => before re-initialising the cache, we must do a purge of the whole  in cache_init()
123 	 * - RPC  in cache_init()
128 		waysize = current_cpu_data.dcache.sets;  in cache_init()
159 		} while (--ways);  in cache_init()
177 	/* Write-through */  in cache_init()
180 	/* Write-back */  in cache_init()
214 		l2_cache_shape = -1; /* No S-cache */  in detect_cache_shape()
297 	current_thread_info()->cpu = hard_smp_processor_id();  in cpu_init()
305 	/* First setup the rest of the I-cache info */  in cpu_init()
306 	current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -  in cpu_init()
309 	current_cpu_data.icache.way_size = current_cpu_data.icache.sets *  in cpu_init()
312 	/* And the D-cache too */  in cpu_init()
313 	current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -  in cpu_init()
316 	current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *  in cpu_init()
325 				       current_cpu_data.dcache.way_size - 1,  in cpu_init()
326 				       PAGE_SIZE - 1);  in cpu_init()
328 		shm_align_mask = PAGE_SIZE - 1;  in cpu_init()
331 		/* Boot CPU sets the cache shape */  in cpu_init()
339 	 * Initialize the per-CPU ASID cache very early, since the  in cpu_init()
340 	 * TLB flushing routines depend on this being setup.  in cpu_init()