Lines Matching +full:0 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define CS5BCR 0xff802050
6 #define CS5WCR 0xff802058
7 #define CS5PCR 0xff802070
14 #define PCMCIA_ATA 0
20 #define PCMCIA_ATTR16 7
22 #define TYPE_SRAM 0
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
26 #define IWW5 0
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
38 #define IWRRS5 0
40 /* burst count (0-3:4,8,16,32) */
41 #define BST5 0
42 #define BST6 0
46 /* RD hold for SRAM (0-1:0,1) */
47 #define RDSPL5 0
48 #define RDSPL6 0
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
50 #define BW5 0
51 #define BW6 0
52 /* Multiplex (0-1:0,1) */
53 #define MPX5 0
54 #define MPX6 0
58 /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
59 #define ADS5 0
60 #define ADS6 0
61 /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
62 #define ADH5 0
63 #define ADH6 0
64 /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
65 #define RDS5 0
66 #define RDS6 0
67 /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
68 #define RDH5 0
69 #define RDH6 0
70 /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
71 #define WTS5 0
72 #define WTS6 0
73 /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
74 #define WTH5 0
75 #define WTH6 0
76 /* BS hold (0-1:1,2) */
77 #define BSH5 0
78 #define BSH6 0
79 /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
83 #define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
84 #define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
85 #define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
86 #define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
87 /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
89 /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
91 /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
93 /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
95 /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
100 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
107 #define SMC0_BASE 0xb0800000 /* eth0 */
108 #define SMC1_BASE 0xb0900000 /* eth1 */
109 #define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
110 #define IDE_BASE 0xb4000000 /* IDE */
111 #define PC104_IO_BASE 0xb8000000
112 #define PC104_MEM_BASE 0xba000000
113 #define SMC_IO_SIZE 0x100
115 #define CF_OFFSET 0x1f0
116 #define IDE_OFFSET 0x170