Lines Matching +full:ext +full:- +full:clk +full:- +full:pin

1 /* SPDX-License-Identifier: GPL-2.0 */
7  * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
8  * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
9  * MODE2: CPG - Reserved (L: Normal operation)
10  * MODE3: CPG - Reserved (L: Normal operation)
11  * MODE4: CPG - Initial PLL setting (72x/36x)
12  * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
13  * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
14  * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
15  * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
16  * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
17  * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
18  * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
19  * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
20  * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
26 /* Pin Function Controller:
27  * GPIO_FN_xx - GPIO used to select pin function
28  * GPIO_Pxx - GPIO mapped to real I/O pin on CPU