Lines Matching +full:chan +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-map-ops.h>
21 #include "pcie-sh7786.h"
45 .name = "PCIe0 MEM 0",
47 .end = 0xfd000000 + SZ_8M - 1,
50 .name = "PCIe0 MEM 1",
52 .end = 0xc0000000 + SZ_512M - 1,
55 .name = "PCIe0 MEM 2",
57 .end = 0x10000000 + SZ_64M - 1,
60 .name = "PCIe0 IO",
62 .end = 0xfe100000 + SZ_1M - 1,
69 .name = "PCIe1 MEM 0",
71 .end = 0xfd800000 + SZ_8M - 1,
74 .name = "PCIe1 MEM 1",
76 .end = 0xa0000000 + SZ_512M - 1,
79 .name = "PCIe1 MEM 2",
81 .end = 0x30000000 + SZ_256M - 1,
84 .name = "PCIe1 IO",
86 .end = 0xfe300000 + SZ_1M - 1,
93 .name = "PCIe2 MEM 0",
95 .end = 0xfc800000 + SZ_4M - 1,
98 .name = "PCIe2 MEM 1",
100 .end = 0x80000000 + SZ_512M - 1,
103 .name = "PCIe2 MEM 2",
105 .end = 0x20000000 + SZ_256M - 1,
108 .name = "PCIe2 IO",
110 .end = 0xfcd00000 + SZ_1M - 1,
142 if (pci_is_root_bus(dev->bus) && dev->devfn == 0) { in sh7786_pci_fixup()
146 dev->resource[i].start = 0; in sh7786_pci_fixup()
147 dev->resource[i].end = 0; in sh7786_pci_fixup()
148 dev->resource[i].flags = 0; in sh7786_pci_fixup()
155 static int __init phy_wait_for_ack(struct pci_channel *chan) in phy_wait_for_ack() argument
159 while (timeout--) { in phy_wait_for_ack()
160 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) in phy_wait_for_ack()
166 return -ETIMEDOUT; in phy_wait_for_ack()
169 static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) in pci_wait_for_irq() argument
173 while (timeout--) { in pci_wait_for_irq()
174 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) in pci_wait_for_irq()
180 return -ETIMEDOUT; in pci_wait_for_irq()
183 static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, in phy_write_reg() argument
192 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); in phy_write_reg()
193 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); in phy_write_reg()
195 phy_wait_for_ack(chan); in phy_write_reg()
198 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); in phy_write_reg()
199 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); in phy_write_reg()
201 phy_wait_for_ack(chan); in phy_write_reg()
206 struct pci_channel *chan = port->hose; in pcie_clk_init() local
223 snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index); in pcie_clk_init()
225 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
226 if (IS_ERR(port->fclk)) { in pcie_clk_init()
227 ret = PTR_ERR(port->fclk); in pcie_clk_init()
231 clk_enable(port->fclk); in pcie_clk_init()
236 clk = &port->phy_clk; in pcie_clk_init()
240 clk->parent = &fixed_pciexclkp; in pcie_clk_init()
241 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
242 clk->enable_bit = BITS_CKE; in pcie_clk_init()
251 clk_disable(port->fclk); in pcie_clk_init()
252 clk_put(port->fclk); in pcie_clk_init()
261 struct pci_channel *chan = port->hose; in phy_init() local
264 clk_enable(&port->phy_clk); in phy_init()
267 phy_write_reg(chan, 0x60, 0xf, 0x004b008b); in phy_init()
268 phy_write_reg(chan, 0x61, 0xf, 0x00007b41); in phy_init()
269 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); in phy_init()
270 phy_write_reg(chan, 0x65, 0xf, 0x09070907); in phy_init()
271 phy_write_reg(chan, 0x66, 0xf, 0x00000010); in phy_init()
272 phy_write_reg(chan, 0x74, 0xf, 0x0007001c); in phy_init()
273 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); in phy_init()
274 phy_write_reg(chan, 0xb0, 0xf, 0x00000610); in phy_init()
277 phy_write_reg(chan, 0x67, 0x1, 0x00000400); in phy_init()
280 clk_disable(&port->phy_clk); in phy_init()
282 while (timeout--) { in phy_init()
283 if (pci_read_reg(chan, SH4A_PCIEPHYSR)) in phy_init()
289 return -ETIMEDOUT; in phy_init()
294 struct pci_channel *chan = port->hose; in pcie_reset() local
296 pci_write_reg(chan, 1, SH4A_PCIESRSTR); in pcie_reset()
297 pci_write_reg(chan, 0, SH4A_PCIETCTLR); in pcie_reset()
298 pci_write_reg(chan, 0, SH4A_PCIESRSTR); in pcie_reset()
299 pci_write_reg(chan, 0, SH4A_PCIETXVC0SR); in pcie_reset()
304 struct pci_channel *chan = port->hose; in pcie_init() local
317 pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1); in pcie_init()
320 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); in pcie_init()
323 if (port->endpoint) in pcie_init()
329 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0); in pcie_init()
332 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3); in pcie_init()
335 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4); in pcie_init()
338 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4); in pcie_init()
341 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5); in pcie_init()
343 data |= (port->index + 1) << 19; in pcie_init()
344 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5); in pcie_init()
347 data = pci_read_reg(chan, SH4A_PCIETLCTLR); in pcie_init()
350 pci_write_reg(chan, data, SH4A_PCIETLCTLR); in pcie_init()
356 data = pci_read_reg(chan, SH4A_PCIEMACCTLR); in pcie_init()
359 pci_write_reg(chan, data, SH4A_PCIEMACCTLR); in pcie_init()
363 memsize = roundup_pow_of_two(memend - memstart); in pcie_init()
371 memsize = roundup_pow_of_two(memend - memstart); in pcie_init()
378 pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1); in pcie_init()
379 pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1, in pcie_init()
386 pci_write_reg(chan, 0, SH4A_PCIELAR1); in pcie_init()
387 pci_write_reg(chan, 0, SH4A_PCIELAMR1); in pcie_init()
394 pci_write_reg(chan, memstart, SH4A_PCIELAR0); in pcie_init()
395 pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0); in pcie_init()
398 data = pci_read_reg(chan, SH4A_PCIETCTLR); in pcie_init()
400 pci_write_reg(chan, data, SH4A_PCIETCTLR); in pcie_init()
406 data = pci_read_reg(chan, SH4A_PCIEDLINTENR); in pcie_init()
408 pci_write_reg(chan, data, SH4A_PCIEDLINTENR); in pcie_init()
411 data = pci_read_reg(chan, SH4A_PCIEMACCTLR); in pcie_init()
413 pci_write_reg(chan, data, SH4A_PCIEMACCTLR); in pcie_init()
420 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL); in pcie_init()
422 data = pci_read_reg(chan, SH4A_PCIEPCICONF1); in pcie_init()
426 pci_write_reg(chan, data, SH4A_PCIEPCICONF1); in pcie_init()
428 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR); in pcie_init()
429 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR); in pcie_init()
434 data = pci_read_reg(chan, SH4A_PCIEMACSR); in pcie_init()
436 port->index, (data >> 20) & 0x3f); in pcie_init()
439 port->index); in pcie_init()
441 for (i = win = 0; i < chan->nr_resources; i++) { in pcie_init()
442 struct resource *res = chan->resources + i; in pcie_init()
447 * We can't use the 32-bit mode windows in legacy 29-bit in pcie_init()
450 if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) in pcie_init()
451 res->flags |= IORESOURCE_DISABLED; in pcie_init()
453 if (res->flags & IORESOURCE_DISABLED) in pcie_init()
456 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); in pcie_init()
463 mask = (roundup_pow_of_two(size) / SZ_256K) - 1; in pcie_init()
464 pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); in pcie_init()
466 pci_write_reg(chan, upper_32_bits(res->start), in pcie_init()
468 pci_write_reg(chan, lower_32_bits(res->start), in pcie_init()
472 if (res->flags & IORESOURCE_IO) in pcie_init()
475 pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win)); in pcie_init()
490 dma_direct_set_offset(&pdev->dev, __pa(memory_start), in pcibios_bus_add_device()
491 __pa(memory_start) - memstart, memsize); in pcibios_bus_add_device()
509 port->endpoint = test_mode_pin(MODE_PIN11); in sh7786_pcie_init_hw()
517 port->index); in sh7786_pcie_init_hw()
524 port->index); in sh7786_pcie_init_hw()
531 port->index); in sh7786_pcie_init_hw()
538 register_pci_controller(port->hose); in sh7786_pcie_init_hw()
556 nr_ports = sh7786_pcie_hwops->core_init(); in sh7786_pcie_init()
560 return -ENODEV; in sh7786_pcie_init()
565 return -ENOMEM; in sh7786_pcie_init()
570 * This is a rather nasty hack for boards with spec-mocking FPGAs in sh7786_pcie_init()
571 * that have a secondary set of clocks outside of the on-chip in sh7786_pcie_init()
598 port->index = i; in sh7786_pcie_init()
599 port->hose = sh7786_pci_channels + i; in sh7786_pcie_init()
600 port->hose->io_map_base = port->hose->resources[0].start; in sh7786_pcie_init()
602 async_schedule(sh7786_pcie_hwops->port_init_hw, port); in sh7786_pcie_init()