42 	return 0;  in arch_uprobe_pre_xol()
58 		return 0;  in check_per_event()
60 	if (control == 0)  in check_per_event()
63 	if ((control & 0x20200000) && (cause & 0x2000))  in check_per_event()
65 	if (cause & 0x8000) {  in check_per_event()
67 		if ((control & 0x80800000) == 0x80000000)  in check_per_event()
70 		if (((control & 0x80800000) == 0x80800000) &&  in check_per_event()
75 	return 0;  in check_per_event()
91 		int reg = (auprobe->insn[0] & 0xf0) >> 4;  in arch_uprobe_post_xol()
96 		int ilen = insn_length(auprobe->insn[0] >> 8);  in arch_uprobe_post_xol()
108 	return 0;  in arch_uprobe_post_xol()
119 	if (regs->int_code & 0x200) /* Trap during transaction */  in arch_uprobe_exception_notify()
178 	int __rc = 0;					\
193 	int __rc = 0;					\
199 	if (__rc == 0)					\
210 	int __rc = 0;					\
221 		psw_bits((regs)->psw).cc = 0;		\
270 	int rc = 0;  in handle_insn_ril()
278 	case 0xc0:  in handle_insn_ril()
280 		case 0x00: /* larl */  in handle_insn_ril()
285 	case 0xc4:  in handle_insn_ril()
287 		case 0x02: /* llhrl */  in handle_insn_ril()
290 		case 0x04: /* lghrl */  in handle_insn_ril()
293 		case 0x05: /* lhrl */  in handle_insn_ril()
296 		case 0x06: /* llghrl */  in handle_insn_ril()
299 		case 0x08: /* lgrl */  in handle_insn_ril()
302 		case 0x0c: /* lgfrl */  in handle_insn_ril()
305 		case 0x0d: /* lrl */  in handle_insn_ril()
308 		case 0x0e: /* llgfrl */  in handle_insn_ril()
311 		case 0x07: /* sthrl */  in handle_insn_ril()
314 		case 0x0b: /* stgrl */  in handle_insn_ril()
317 		case 0x0f: /* strl */  in handle_insn_ril()
322 	case 0xc6:  in handle_insn_ril()
324 		case 0x04: /* cghrl */  in handle_insn_ril()
327 		case 0x05: /* chrl */  in handle_insn_ril()
330 		case 0x06: /* clghrl */  in handle_insn_ril()
333 		case 0x07: /* clhrl */  in handle_insn_ril()
336 		case 0x08: /* cgrl */  in handle_insn_ril()
339 		case 0x0a: /* clgrl */  in handle_insn_ril()
342 		case 0x0c: /* cgfrl */  in handle_insn_ril()
345 		case 0x0d: /* crl */  in handle_insn_ril()
348 		case 0x0e: /* clgfrl */  in handle_insn_ril()
351 		case 0x0f: /* clrl */  in handle_insn_ril()
360 		regs->int_code = ilen << 16 | 0x0001;  in handle_insn_ril()
364 		regs->int_code = ilen << 16 | 0x0006;  in handle_insn_ril()
368 		regs->int_code = ilen << 16 | 0x0005;  in handle_insn_ril()