Lines Matching +full:64 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
9 * bit first (BE).
16 #include <asm/nospec-insn.h>
17 #include <asm/vx-insn.h>
19 /* Vector register range containing CRC-32 constants */
31 * The CRC-32 constant block contains reduction constants to fold and
34 * For the CRC-32 variants, the constants are precomputed according to
37 * R1 = x4*128+64 mod P(x)
39 * R3 = x128+64 mod P(x)
44 * Barret reduction constant, u, is defined as floor(x**64 / P(x)).
55 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
75 * The CRC-32 function(s) use these calling conventions:
82 * %r4: Length of the buffer, must be 64 bytes or greater.
86 * %r5: CRC-32 constant pool base pointer.
91 * V9..V14: CRC-32 constants.
94 /* Load CRC-32 constants */
102 /* Load a 64-byte data chunk and XOR with CRC */
103 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
105 aghi %r3,64 /* BUF = BUF + 64 */
106 aghi %r4,-64 /* LEN = LEN - 64 */
109 cghi %r4,64
113 /* Load the next 64-byte data chunk into V5 to V8 */
129 aghi %r3,64 /* BUF = BUF + 64 */
130 aghi %r4,-64 /* LEN = LEN - 64 */
132 cghi %r4,64
136 /* Fold V1 to V4 into a single 128-bit value in V1 */
141 /* Check whether to continue with 64-bit folding */
152 aghi %r4,-16
160 * The R5 constant is used to fold a 128-bit value into an 96-bit value
161 * that is XORed with the next 96-bit input data chunk. To use a single
162 * VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to
163 * form an intermediate 96-bit value (with appended zeros) which is then
169 * Further reduce the remaining 96-bit value to a 64-bit value using a
172 * doubleword with R6. The result is a 64-bit value and is subject to
178 * The input values to the Barret reduction are the degree-63 polynomial
179 * in V1 (R(x)), degree-32 generator polynomial, and the reduction