Lines Matching +full:timebase +full:- +full:frequency
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-icicle-kit-fabric.dtsi"
9 /* Clock frequency (in Hz) of the rtcclk */
13 model = "Microchip PolarFire-SoC Icicle Kit";
14 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
27 stdout-path = "serial1:115200n8";
31 timebase-frequency = <RTCCLK_FREQ>;
46 reserved-memory {
47 #address-cells = <2>;
48 #size-cells = <2>;
53 no-map;
87 phy-mode = "sgmii";
88 phy-handle = <&phy0>;
93 phy-mode = "sgmii";
94 phy-handle = <&phy1>;
97 phy1: ethernet-phy@9 {
101 phy0: ethernet-phy@8 {
111 bus-width = <4>;
112 disable-wp;
113 cap-sd-highspeed;
114 cap-mmc-highspeed;
115 mmc-ddr-1_8v;
116 mmc-hs200-1_8v;
117 sd-uhs-sdr12;
118 sd-uhs-sdr25;
119 sd-uhs-sdr50;
120 sd-uhs-sdr104;
149 clock-frequency = <125000000>;