Lines Matching +full:0 +full:x200000

34 		#size-cells = <0>;
36 		cpu0: cpu@0 {
39 			reg = <0>;
43 			i-cache-size = <0x8000>;
45 			d-cache-size = <0x8000>;
59 			i-cache-size = <0x8000>;
61 			d-cache-size = <0x8000>;
84 		reg = <0x80000000 0x400000>, /* sram0 4 MiB */
85 		      <0x80400000 0x200000>, /* sram1 2 MiB */
86 		      <0x80600000 0x200000>; /* aisram 2 MiB */
100 			#clock-cells = <0>;
113 			reg = <0x1000 0x1000>;
119 			reg = <0x2000000 0xC000>;
126 			#address-cells = <0>;
127 			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
128 			reg = <0xC000000 0x4000000>;
137 			reg = <0x38000000 0x1000>;
146 			reg = <0x38001000 0x1000>;
159 			reg = <0x50000000 0x1000>;
167 			snps,priority = <0 1 2 3 4 5>;
169 			snps,block-size = <0x200000 0x200000 0x200000
170 					   0x200000 0x200000 0x200000>;
178 			ranges = <0x50200000 0x50200000 0x200000>;
183 				#size-cells = <0>;
185 				reg = <0x50200000 0x80>;
191 				gpio1_0: gpio-port@0 {
195 					reg = <0>;
205 				reg = <0x50210000 0x100>;
221 				reg = <0x50220000 0x100>;
237 				reg = <0x50230000 0x100>;
254 				reg = <0x50240000 0x100>;
255 				#address-cells = <0>;
256 				#size-cells = <0>;
267 				reg = <0x50250000 0x200>;
276 				reg = <0x50260000 0x200>;
285 				reg = <0x50270000 0x200>;
294 				reg = <0x50280000 0x100>;
304 				reg = <0x50290000 0x100>;
314 				reg = <0x502A0000 0x100>;
324 				reg = <0x502B0000 0x100>;
334 				reg = <0x502D0000 0x14>;
344 				reg = <0x502D0014 0x14>;
354 				reg = <0x502E0000 0x14>;
364 				reg = <0x502E0014 0x114>;
374 				reg = <0x502F0000 0x14>;
384 				reg = <0x502F0014 0x14>;
397 			ranges = <0x50400000 0x50400000 0x40100>;
402 				reg = <0x50400000 0x100>;
412 				reg = <0x50410000 0x100>;
423 				reg = <0x50440000 0x100>;
452 			ranges = <0x52000000 0x52000000 0x2000200>;
457 				#size-cells = <0>;
459 				reg = <0x52000000 0x100>;
472 				#size-cells = <0>;
474 				reg = <0x53000000 0x100>;
487 				#size-cells = <0>;
489 				reg = <0x54000000 0x200>;