Lines Matching full:31
1018 else if (value >= 24 && value <= 31) in insert_rx()
1047 else if (value >= 24 && value <= 31) in insert_ry()
1589 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) in insert_mbe()
1630 ret |= 1L << (31 - i); in extract_mbe()
1638 ret &= ~(1L << (31 - i)); in extract_mbe()
3159 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3161 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3688 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3748 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4593 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4594 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4597 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4598 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4605 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4608 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4656 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4657 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4658 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4659 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4661 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4662 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4663 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4664 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4665 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4666 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4667 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4668 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4669 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4670 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4671 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4672 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4673 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4674 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4675 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4676 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4677 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4678 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4679 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4680 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4681 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4682 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4683 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4684 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4685 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4686 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4687 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4688 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4689 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4690 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4691 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4692 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4693 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4695 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4696 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4697 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4699 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4700 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4701 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4702 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4703 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4704 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4706 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4707 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4709 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4710 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4711 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4712 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4714 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4715 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4717 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4719 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4721 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4722 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4723 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4724 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4726 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4727 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4729 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4731 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4733 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4735 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4736 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4738 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4739 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4740 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4741 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4743 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4744 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4745 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4746 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4748 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4749 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4751 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4752 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4754 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4755 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4757 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4759 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4760 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4762 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4764 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4765 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4766 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4767 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4769 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4770 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4771 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4773 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4775 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4777 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4779 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4781 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4783 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4785 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4787 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4788 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4789 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4790 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4792 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4793 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4794 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4795 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4797 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4799 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4801 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4803 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4804 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4806 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4807 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4809 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4810 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4812 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4813 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4814 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4816 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4818 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4819 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4820 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4821 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4822 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4823 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4824 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4825 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4826 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4827 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4828 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4829 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4830 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4831 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4832 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4833 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4835 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4836 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4837 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4839 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4840 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4842 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4843 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4845 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4847 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4849 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4851 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4852 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4854 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4856 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4858 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4860 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4861 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4863 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4864 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4866 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4867 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4869 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4871 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4873 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4874 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4875 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4877 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4879 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4881 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4883 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4885 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4886 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4887 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4888 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4890 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4892 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4894 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4896 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4898 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4899 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4901 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4902 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4903 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4904 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4906 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4907 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4908 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4909 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4911 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4913 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4914 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4916 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4917 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4918 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4920 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4922 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
4924 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4925 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4927 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4929 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4931 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4932 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4934 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4935 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
4937 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4938 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
4940 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
4942 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4944 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4946 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
4948 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4950 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4951 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4953 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4955 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4956 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4958 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
4960 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4961 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4962 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4963 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
4965 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
4967 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4968 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
4970 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4971 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4973 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
4974 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
4976 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
4978 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
4980 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
4982 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4983 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4985 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4986 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4987 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4988 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4990 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4991 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4992 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4993 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4995 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
4997 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
4999 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5000 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5001 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5002 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
5004 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5006 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5008 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5010 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5011 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5013 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5014 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5016 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5018 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5020 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5022 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5023 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5025 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5026 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5027 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5028 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5030 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5031 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5033 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5034 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5035 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5036 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5038 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5039 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5040 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5041 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5043 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5044 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5045 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5046 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5048 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5049 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5050 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5052 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5053 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5054 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5055 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5057 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5059 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5060 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5062 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5064 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5066 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5067 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
5069 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5071 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5073 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5075 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5076 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5077 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5079 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5081 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5082 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5083 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5084 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5086 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5088 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5089 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5091 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
5093 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5094 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
5096 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5098 {"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
5100 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5101 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5103 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5104 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5105 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5106 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5108 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5110 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
5112 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5113 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5115 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5117 {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
5119 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5120 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5122 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5124 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5126 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5127 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5128 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5129 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5131 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5133 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5135 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5137 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5139 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5141 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5142 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5144 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5146 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5147 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5148 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5149 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5150 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5151 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5152 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5153 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5154 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5155 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5156 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5157 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5158 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5159 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5160 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5161 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5162 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5163 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5164 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5165 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5166 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5167 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5168 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5169 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5170 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5171 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5172 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5173 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5174 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5175 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5176 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5177 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5178 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5179 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5180 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5181 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5183 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5185 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5187 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5188 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5190 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5192 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5193 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5195 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5197 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5198 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5199 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5200 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5201 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5202 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5203 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5204 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5205 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5206 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5207 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5208 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5209 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5210 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5211 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5212 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5213 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5214 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5215 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5216 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5217 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5218 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5219 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5220 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5221 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5222 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5223 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5224 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5225 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5226 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5227 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5228 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5229 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5230 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5231 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5232 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5233 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5234 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5235 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5236 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5237 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5238 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5239 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5240 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5241 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5242 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5243 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5244 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5245 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5246 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5247 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5248 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5249 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5250 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5251 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5252 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5253 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5254 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5255 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5256 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5257 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5258 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5259 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5260 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5261 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5262 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5263 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5264 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5265 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5266 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5267 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5268 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5269 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5270 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5271 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5272 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5273 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5274 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5275 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5276 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5277 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5278 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5279 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5280 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5281 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5282 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5283 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5284 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5285 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5286 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5287 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5288 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5289 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5290 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5291 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5292 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5293 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5294 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5295 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5296 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5297 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5298 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5299 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5300 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5301 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5302 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5303 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5304 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5305 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5306 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5307 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5308 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5309 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5310 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5311 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5312 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5313 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5314 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5315 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5316 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5317 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5318 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5319 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5320 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5321 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5322 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5323 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5324 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5325 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5326 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5327 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5328 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5329 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5330 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5331 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5332 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5333 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5334 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5335 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5336 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5337 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5338 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5339 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5340 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5341 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5342 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5343 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5344 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5345 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5346 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5347 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5348 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5349 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5350 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5351 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5352 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5353 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5354 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5355 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5356 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5357 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5358 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5359 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5360 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5361 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5362 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5363 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5364 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5365 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5366 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5367 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5368 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5369 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5370 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5371 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5372 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5373 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5374 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5375 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5376 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5377 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5378 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5379 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5380 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5381 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5382 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5383 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5384 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5385 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5386 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5387 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5388 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5389 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5390 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5391 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5392 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5393 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5394 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5395 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5396 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5397 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5399 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5401 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5403 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5405 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5407 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5408 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5410 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5411 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5413 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5415 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5417 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5418 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5419 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5421 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5423 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5425 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5427 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5429 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5430 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5432 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5434 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5435 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5437 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5438 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5439 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5440 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5442 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5443 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5445 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5447 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5449 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5451 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5453 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5454 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5456 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5458 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5459 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5461 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5463 {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5465 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5467 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5469 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5470 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5471 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5472 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5474 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5476 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5478 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5480 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5482 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5484 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5495 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5496 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5497 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5498 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5500 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5501 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5502 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5503 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5504 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5505 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5506 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5507 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5508 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5509 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5510 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5511 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5512 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5513 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5514 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5515 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5516 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5517 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5518 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5519 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5520 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5521 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5522 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5523 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5524 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5525 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5526 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5527 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5528 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5529 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5530 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5531 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5532 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5533 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5534 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5535 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5537 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5539 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5540 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5542 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5543 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5545 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5546 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5548 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5549 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5551 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5553 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5554 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5555 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5556 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5557 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5558 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5559 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5560 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5561 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5562 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5563 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5564 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5565 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5566 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5567 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5568 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5569 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5570 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5571 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5572 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5573 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5574 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5575 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5576 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5577 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5578 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5579 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5580 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5581 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5582 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5583 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5584 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5585 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5586 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5587 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5588 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5589 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5590 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5591 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5592 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5593 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5594 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5595 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5596 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5597 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5598 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5599 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5600 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5601 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5602 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5603 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5604 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5605 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5606 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5607 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5608 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5609 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5610 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5611 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5612 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5613 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5614 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5615 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5616 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5617 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5618 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5619 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5620 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5621 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5622 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5623 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5624 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5625 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5626 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5627 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5628 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5629 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5630 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5631 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5632 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5633 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5634 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5635 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5636 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5637 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5638 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5639 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5640 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5641 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5642 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5643 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5644 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5645 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5646 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5647 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5648 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5649 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5650 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5651 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5652 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5653 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5654 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5655 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5656 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5657 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5658 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5659 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5660 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5661 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5662 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5663 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5664 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5665 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5666 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5667 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5668 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5669 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5670 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5671 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5672 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5673 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5674 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5675 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5676 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5677 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5678 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5679 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5680 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5681 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5682 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5683 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5684 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5685 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5686 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5687 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5688 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5689 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5690 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5691 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5692 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5693 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5694 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5695 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5696 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5697 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5698 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5699 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5700 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5701 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5702 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5703 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5704 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5705 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5706 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5707 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5708 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5709 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5710 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5711 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5712 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5713 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5714 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5715 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5716 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5717 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5719 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5721 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5722 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5724 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5726 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5728 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5730 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5732 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5733 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5735 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5736 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5738 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5739 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5741 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5743 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5744 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5746 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5748 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5750 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5752 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5754 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5755 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5757 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
5759 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5760 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5762 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5763 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5764 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5765 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5766 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5767 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5769 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5770 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5771 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5772 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5774 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5776 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
5778 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5780 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5781 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5783 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5784 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5786 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5788 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5789 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5790 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5791 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5793 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5794 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
5796 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5797 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
5799 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5800 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5802 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5803 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
5805 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5806 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5808 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5810 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
5812 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5813 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5815 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5816 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5817 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5818 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5820 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
5822 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5824 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5825 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
5827 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
5829 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5830 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5832 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5834 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
5836 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5838 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5840 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5842 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5843 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
5845 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5846 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5847 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5848 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5849 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5850 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5851 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5852 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5853 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
5855 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5857 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5858 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
5860 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5862 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5864 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
5866 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5868 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5869 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
5871 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5872 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5874 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5876 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
5878 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5880 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5881 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
5883 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5884 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5886 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5888 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5890 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5891 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5892 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5893 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5895 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5896 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5897 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5898 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5900 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5902 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
5904 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5905 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5907 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5908 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5910 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5912 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5913 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
5915 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5916 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
5918 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
5919 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
5921 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5923 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5924 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5926 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5927 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5929 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5931 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5933 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5934 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
5936 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
5937 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
5939 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5941 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
5943 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5945 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
5947 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5949 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5950 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5951 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5952 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5954 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5955 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5956 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5957 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5959 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5960 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
5962 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5964 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5966 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5967 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
5969 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5970 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
5972 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5973 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
5975 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
5977 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5979 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
5981 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5983 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5984 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5985 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5986 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5988 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5989 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5991 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5992 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5993 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5994 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5996 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5997 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5998 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5999 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6001 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6002 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6003 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
6005 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6007 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6008 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6010 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6012 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6013 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6015 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6017 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6019 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6020 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6021 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6023 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6024 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6026 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6027 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6028 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6029 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6031 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6032 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6034 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6035 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6037 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6039 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6041 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6043 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6045 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6046 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6048 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6049 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6050 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6051 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6053 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6054 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6056 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6058 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6059 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6060 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6062 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6063 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6065 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6067 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6069 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6071 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6073 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
6075 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6077 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6078 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6079 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6080 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6082 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6083 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6085 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6087 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
6089 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6090 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6092 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6093 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6095 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6097 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6099 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6100 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6101 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6103 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6105 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6106 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6107 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6108 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
6110 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6112 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6114 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6115 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6117 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6118 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6120 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6122 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6124 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6126 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6128 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
6130 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6132 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6133 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6135 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6137 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6138 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6140 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6141 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6142 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6143 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6145 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6146 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6148 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6150 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6151 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6153 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6154 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6156 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6158 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6160 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6161 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6163 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6164 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6166 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6167 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6169 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6170 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6171 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6172 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
6174 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6176 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6178 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6179 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6180 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
6182 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6184 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6185 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6186 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6187 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6189 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6190 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6192 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6194 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6195 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6196 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6198 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6200 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6201 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6203 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6205 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6206 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
6208 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6209 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
6211 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6213 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6214 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6216 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6217 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6219 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6220 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6222 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6223 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6225 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6226 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6227 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6228 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6230 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6232 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6234 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6236 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6238 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6239 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
6241 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6243 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6245 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6247 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6248 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6250 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6251 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6253 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6254 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6256 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6258 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6260 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6262 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6264 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6265 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6267 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6269 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6275 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6276 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6277 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
6392 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6393 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6650 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6758 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6759 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6760 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6761 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7146 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7147 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7148 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7149 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7150 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7151 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7152 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7153 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7154 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7155 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7156 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7158 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7160 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7161 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7163 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7164 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7166 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7167 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7169 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7171 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7172 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7174 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7176 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7177 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7215 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7216 when x=0; 32-x when x is between 1 and 31; are negative if x is
7245 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7246 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7247 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7248 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7251 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7252 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7253 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7254 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7255 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7256 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7257 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7258 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7259 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7260 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7261 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7262 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7263 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7264 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7267 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7268 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7270 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7271 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7272 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7273 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7274 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7275 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7276 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},