Lines Matching +full:four +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
24 #include <linux/dma-mapping.h>
39 #undef DEBUG_PW /* Port-Write debugging */
78 "3: li %1,-1\n" \
84 : "b" (addr), "i" (-EFAULT), "0" (err))
113 entry = search_exception_tables(regs->nip); in fsl_rio_mcheck_exception()
115 pr_debug("RIO: %s - MC Exception handled\n", in fsl_rio_mcheck_exception()
131 * fsl_local_config_read - Generate a MPC85xx local config space read
139 * success or %-EINVAL on failure.
144 struct rio_priv *priv = mport->priv; in fsl_local_config_read()
147 *data = in_be32(priv->regs_win + offset); in fsl_local_config_read()
153 * fsl_local_config_write - Generate a MPC85xx local config space write
161 * success or %-EINVAL on failure.
166 struct rio_priv *priv = mport->priv; in fsl_local_config_write()
170 out_be32(priv->regs_win + offset, data); in fsl_local_config_write()
176 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
186 * success or %-EINVAL on failure.
192 struct rio_priv *priv = mport->priv; in fsl_rio_config_read()
204 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) in fsl_rio_config_read()
205 return -EINVAL; in fsl_rio_config_read()
209 out_be32(&priv->maint_atmu_regs->rowtar, in fsl_rio_config_read()
211 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); in fsl_rio_config_read()
213 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); in fsl_rio_config_read()
226 return -EINVAL; in fsl_rio_config_read()
241 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
251 * success or %-EINVAL on failure.
257 struct rio_priv *priv = mport->priv; in fsl_rio_config_write()
269 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) in fsl_rio_config_write()
270 return -EINVAL; in fsl_rio_config_write()
274 out_be32(&priv->maint_atmu_regs->rowtar, in fsl_rio_config_write()
276 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); in fsl_rio_config_write()
278 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); in fsl_rio_config_write()
290 ret = -EINVAL; in fsl_rio_config_write()
303 out_be32(&priv->inb_atmu_regs[i].riwar, 0); in fsl_rio_inbound_mem_init()
309 struct rio_priv *priv = mport->priv; in fsl_map_inb_mem()
316 if ((size & (size - 1)) != 0 || size > 0x400000000ULL) in fsl_map_inb_mem()
317 return -EINVAL; in fsl_map_inb_mem()
323 if (lstart & (base_size - 1)) in fsl_map_inb_mem()
324 return -EINVAL; in fsl_map_inb_mem()
325 if (rstart & (base_size - 1)) in fsl_map_inb_mem()
326 return -EINVAL; in fsl_map_inb_mem()
330 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
333 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK)) in fsl_map_inb_mem()
335 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1); in fsl_map_inb_mem()
337 return -EINVAL; in fsl_map_inb_mem()
342 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
347 return -ENOMEM; in fsl_map_inb_mem()
349 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT); in fsl_map_inb_mem()
350 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT); in fsl_map_inb_mem()
351 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL | in fsl_map_inb_mem()
352 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1)); in fsl_map_inb_mem()
360 struct rio_priv *priv = mport->priv; in fsl_unmap_inb_mem()
367 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_unmap_inb_mem()
371 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar); in fsl_unmap_inb_mem()
374 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE); in fsl_unmap_inb_mem()
415 str = "Single-lane 0"; in fsl_rio_info()
418 str = "Single-lane 2"; in fsl_rio_info()
421 str = "Four-lane"; in fsl_rio_info()
431 dev_info(dev, "Output port operating in 8-bit mode\n"); in fsl_rio_info()
433 dev_info(dev, "Input port operating in 8-bit mode\n"); in fsl_rio_info()
438 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
442 * master port with system-specific info, and registers the
463 if (!dev->dev.of_node) { in fsl_rio_setup()
464 dev_err(&dev->dev, "Device OF-Node is NULL"); in fsl_rio_setup()
465 return -ENODEV; in fsl_rio_setup()
468 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); in fsl_rio_setup()
470 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", in fsl_rio_setup()
471 dev->dev.of_node); in fsl_rio_setup()
472 return -EFAULT; in fsl_rio_setup()
474 dev_info(&dev->dev, "Of-device full name %pOF\n", in fsl_rio_setup()
475 dev->dev.of_node); in fsl_rio_setup()
476 dev_info(&dev->dev, "Regs: %pR\n", ®s); in fsl_rio_setup()
480 dev_err(&dev->dev, "Unable to map rio register window\n"); in fsl_rio_setup()
481 rc = -ENOMEM; in fsl_rio_setup()
487 rc = -ENOMEM; in fsl_rio_setup()
490 ops->lcread = fsl_local_config_read; in fsl_rio_setup()
491 ops->lcwrite = fsl_local_config_write; in fsl_rio_setup()
492 ops->cread = fsl_rio_config_read; in fsl_rio_setup()
493 ops->cwrite = fsl_rio_config_write; in fsl_rio_setup()
494 ops->dsend = fsl_rio_doorbell_send; in fsl_rio_setup()
495 ops->pwenable = fsl_rio_pw_enable; in fsl_rio_setup()
496 ops->open_outb_mbox = fsl_open_outb_mbox; in fsl_rio_setup()
497 ops->open_inb_mbox = fsl_open_inb_mbox; in fsl_rio_setup()
498 ops->close_outb_mbox = fsl_close_outb_mbox; in fsl_rio_setup()
499 ops->close_inb_mbox = fsl_close_inb_mbox; in fsl_rio_setup()
500 ops->add_outb_message = fsl_add_outb_message; in fsl_rio_setup()
501 ops->add_inb_buffer = fsl_add_inb_buffer; in fsl_rio_setup()
502 ops->get_inb_message = fsl_get_inb_message; in fsl_rio_setup()
503 ops->map_inb = fsl_map_inb_mem; in fsl_rio_setup()
504 ops->unmap_inb = fsl_unmap_inb_mem; in fsl_rio_setup()
506 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0); in fsl_rio_setup()
508 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n"); in fsl_rio_setup()
509 rc = -ENOENT; in fsl_rio_setup()
514 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", in fsl_rio_setup()
522 dev_err(&dev->dev, "Unable to map rmu register window\n"); in fsl_rio_setup()
523 rc = -ENOMEM; in fsl_rio_setup()
526 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") { in fsl_rio_setup()
532 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit"); in fsl_rio_setup()
534 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n"); in fsl_rio_setup()
535 rc = -ENODEV; in fsl_rio_setup()
540 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n"); in fsl_rio_setup()
541 rc = -ENOMEM; in fsl_rio_setup()
544 dbell->dev = &dev->dev; in fsl_rio_setup()
545 dbell->bellirq = irq_of_parse_and_map(np, 1); in fsl_rio_setup()
546 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq); in fsl_rio_setup()
553 rc = -ENOMEM; in fsl_rio_setup()
557 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win + in fsl_rio_setup()
561 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit"); in fsl_rio_setup()
563 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n"); in fsl_rio_setup()
564 rc = -ENODEV; in fsl_rio_setup()
569 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n"); in fsl_rio_setup()
570 rc = -ENOMEM; in fsl_rio_setup()
573 pw->dev = &dev->dev; in fsl_rio_setup()
574 pw->pwirq = irq_of_parse_and_map(np, 0); in fsl_rio_setup()
575 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq); in fsl_rio_setup()
581 rc = -ENOMEM; in fsl_rio_setup()
585 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start); in fsl_rio_setup()
588 for_each_child_of_node(dev->dev.of_node, np) { in fsl_rio_setup()
589 port_index = of_get_property(np, "cell-index", NULL); in fsl_rio_setup()
591 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n", in fsl_rio_setup()
598 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n", in fsl_rio_setup()
604 cell = of_get_property(np, "#address-cells", NULL); in fsl_rio_setup()
610 cell = of_get_property(np, "#size-cells", NULL); in fsl_rio_setup()
620 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n", in fsl_rio_setup()
633 i = *port_index - 1; in fsl_rio_setup()
634 port->index = (unsigned char)i; in fsl_rio_setup()
638 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n"); in fsl_rio_setup()
643 INIT_LIST_HEAD(&port->dbells); in fsl_rio_setup()
644 port->iores.start = range_start; in fsl_rio_setup()
645 port->iores.end = port->iores.start + range_size - 1; in fsl_rio_setup()
646 port->iores.flags = IORESOURCE_MEM; in fsl_rio_setup()
647 port->iores.name = "rio_io_win"; in fsl_rio_setup()
649 if (request_resource(&iomem_resource, &port->iores) < 0) { in fsl_rio_setup()
650 dev_err(&dev->dev, "RIO: Error requesting master port region" in fsl_rio_setup()
651 " 0x%016llx-0x%016llx\n", in fsl_rio_setup()
652 (u64)port->iores.start, (u64)port->iores.end); in fsl_rio_setup()
657 sprintf(port->name, "RIO mport %d", i); in fsl_rio_setup()
659 priv->dev = &dev->dev; in fsl_rio_setup()
660 port->dev.parent = &dev->dev; in fsl_rio_setup()
661 port->ops = ops; in fsl_rio_setup()
662 port->priv = priv; in fsl_rio_setup()
663 port->phys_efptr = 0x100; in fsl_rio_setup()
664 port->phys_rmap = 1; in fsl_rio_setup()
665 priv->regs_win = rio_regs_win; in fsl_rio_setup()
667 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); in fsl_rio_setup()
670 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) { in fsl_rio_setup()
671 dev_err(&dev->dev, "Port %d is not ready. " in fsl_rio_setup()
674 out_be32(priv->regs_win in fsl_rio_setup()
676 /* Set 1x lane */ in fsl_rio_setup()
677 setbits32(priv->regs_win in fsl_rio_setup()
680 setbits32(priv->regs_win in fsl_rio_setup()
683 if (in_be32((priv->regs_win in fsl_rio_setup()
685 dev_err(&dev->dev, in fsl_rio_setup()
687 release_resource(&port->iores); in fsl_rio_setup()
692 dev_info(&dev->dev, "Port %d restart success!\n", i); in fsl_rio_setup()
694 fsl_rio_info(&dev->dev, ccsr); in fsl_rio_setup()
696 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) in fsl_rio_setup()
698 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", in fsl_rio_setup()
699 port->sys_size ? 65536 : 256); in fsl_rio_setup()
701 if (port->host_deviceid >= 0) in fsl_rio_setup()
702 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | in fsl_rio_setup()
705 out_be32(priv->regs_win + RIO_GCCSR, in fsl_rio_setup()
708 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win in fsl_rio_setup()
712 priv->maint_atmu_regs = priv->atmu_regs + 1; in fsl_rio_setup()
713 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *) in fsl_rio_setup()
714 (priv->regs_win + in fsl_rio_setup()
719 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80), in fsl_rio_setup()
723 out_be32(&priv->maint_atmu_regs->rowbar, in fsl_rio_setup()
724 port->iores.start >> 12); in fsl_rio_setup()
725 out_be32(&priv->maint_atmu_regs->rowar, in fsl_rio_setup()
726 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); in fsl_rio_setup()
728 priv->maint_win = ioremap(port->iores.start, in fsl_rio_setup()
736 dbell->mport[i] = port; in fsl_rio_setup()
737 pw->mport[i] = port; in fsl_rio_setup()
740 release_resource(&port->iores); in fsl_rio_setup()
749 rc = -ENOLINK; in fsl_rio_setup()
775 /* The probe function for RapidIO peer-to-peer network.
779 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n", in fsl_of_rio_rpn_probe()
780 dev->dev.of_node); in fsl_of_rio_rpn_probe()
794 .name = "fsl-of-rio",