Lines Matching refs:spu_pdata

107 struct spu_pdata {  struct
116 static struct spu_pdata *spu_pdata(struct spu *spu) in spu_pdata() argument
136 return spu_pdata(arg)->spe_id; in ps3_get_spe_id()
159 &spu_pdata(spu)->priv2_addr, &problem_phys, in construct_spu()
161 &spu_pdata(spu)->shadow_addr, in construct_spu()
162 &spu_pdata(spu)->spe_id); in construct_spu()
180 iounmap(spu_pdata(spu)->shadow); in spu_unmap()
195 spu_pdata(spu)->shadow = ioremap_prot(spu_pdata(spu)->shadow_addr, in setup_areas()
197 if (!spu_pdata(spu)->shadow) { in setup_areas()
218 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr, in setup_areas()
226 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr, in setup_areas()
228 spu_pdata(spu)->shadow_addr); in setup_areas()
229 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2, in setup_areas()
231 (unsigned long)spu_pdata(spu)->shadow); in setup_areas()
245 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, in setup_interrupts()
251 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, in setup_interrupts()
257 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, in setup_interrupts()
278 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id, in enable_spu()
279 spu_pdata(spu)->resource_id); in enable_spu()
302 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); in enable_spu()
313 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); in ps3_destroy_spu()
324 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id); in ps3_destroy_spu()
339 spu->pdata = kzalloc(sizeof(struct spu_pdata), in ps3_create_spu()
347 spu_pdata(spu)->resource_id = (unsigned long)data; in ps3_create_spu()
351 spu_pdata(spu)->cache.sr1 = 0x33; in ps3_create_spu()
368 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status) in ps3_create_spu()
481 spu_pdata(spu)->cache.masks[class] = mask; in int_mask_set()
482 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class, in int_mask_set()
483 spu_pdata(spu)->cache.masks[class]); in int_mask_set()
488 return spu_pdata(spu)->cache.masks[class]; in int_mask_get()
495 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class, in int_stat_clear()
503 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat); in int_stat_get()
514 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW); in mfc_dar_get()
524 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW); in mfc_dsisr_get()
539 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); in mfc_sr1_set()
541 spu_pdata(spu)->cache.sr1 = sr1; in mfc_sr1_set()
543 spu_pdata(spu)->spe_id, in mfc_sr1_set()
545 spu_pdata(spu)->cache.sr1); in mfc_sr1_set()
550 return spu_pdata(spu)->cache.sr1; in mfc_sr1_get()
555 spu_pdata(spu)->cache.tclass_id = tclass_id; in mfc_tclass_id_set()
557 spu_pdata(spu)->spe_id, in mfc_tclass_id_set()
559 spu_pdata(spu)->cache.tclass_id); in mfc_tclass_id_set()
564 return spu_pdata(spu)->cache.tclass_id; in mfc_tclass_id_get()