Lines Matching full:windows

30  * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports,
47  * The HVWCs for all windows on a specific instance of VAS are in a contiguous
49  * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance
89  *	 credits? Its NA for NX but may be needed for other receive windows.
227  * to a paste command and hence applies only to receive windows.
269  * Local Notify Scope Control Register. (Receive windows only).
279  * Local DMA Cache Control Register (Receive windows only).
287  * Local Notify Scope Control Register. (Receive windows only).
288  * Not applicable to NX receive windows.
314  * receive windows, one per coprocessor type.
316  * See also function header of set_vinst_win() for details on ->windows[]
341 	struct pnv_vas_window *windows[VAS_WINDOWS_PER_CHIP];  member
353 	/* Fields common to send and receive windows */
361 	/* Fields applicable only to send windows */
366 	/* Fields applicable only to receive windows */