57 #define BANDIT_MAGIC	0x50
58 #define BANDIT_COHERENT	0x40
127 	| (((unsigned int)(off)) & 0xFCUL))
132 	|(((unsigned int)(off)) & 0xFCUL) \
158 	offset &= has_uninorth ? 0x07 : 0x03;  in macrisc_cfg_map_bus()
179 	if (offset >= 0x100)  in chaos_map_bus()
190 	if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)  in chaos_map_bus()
191 	    && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))  in chaos_map_bus()
209 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_chaos()
210 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_chaos()
223  *  0 -> No special case
225  *       (return 0xff's on reads, eventually, cache config space
242 	else if (devfn == 0)  in u3_ht_skip_device()
243 		return 0;  in u3_ht_skip_device()
256 	for (i=0; i<2; i++)  in u3_ht_skip_device()
260 	return 0;  in u3_ht_skip_device()
268 		+ 0x01000000UL)
275 		if (devfn != 0)  in u3_ht_cfg_access()
277 		*swap = 0;  in u3_ht_cfg_access()
293 	if (offset >= 0x100)  in u3_ht_read_config()
300 	case 0:  in u3_ht_read_config()
305 			*val = 0xff; break;  in u3_ht_read_config()
307 			*val = 0xffff; break;  in u3_ht_read_config()
309 			*val = 0xfffffffful; break;  in u3_ht_read_config()
344 	if (offset >= 0x100)  in u3_ht_write_config()
351 	case 0:  in u3_ht_write_config()
387 	 | (((unsigned int)(off)) & 0xfcU))
393 	 |(((unsigned int)(off)) & 0xfcU)	\
403 	if (offset >= 0x1000)  in u4_pcie_cfg_map_bus()
420 	offset &= 0x03;  in u4_pcie_cfg_map_bus()
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
457 	/* read the word at offset 0 in config space for device 11 */  in init_bandit()
476 	/* read the word at offset 0x50 */  in init_bandit()
480 	if ((magic & BANDIT_COHERENT) != 0)  in init_bandit()
503 	if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {  in init_p2pbridge()
516 				   PCI_BRIDGE_CONTROL, &val) < 0) {  in init_p2pbridge()
539 	if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {  in init_second_ohare()
575 		if (0x1033 != *prop)  in fixup_nec_usb2()
580 		if (0x0035 != *prop)  in fixup_nec_usb2()
585 		devfn = (prop[0] >> 8) & 0xff;  in fixup_nec_usb2()
586 		bus = (prop[0] >> 16) & 0xff;  in fixup_nec_usb2()
587 		if (PCI_FUNC(devfn) != 0)  in fixup_nec_usb2()
592 		early_read_config_dword(hose, bus, devfn, 0xe4, &data);  in fixup_nec_usb2()
597 			early_write_config_dword(hose, bus, devfn, 0xe4, data);  in fixup_nec_usb2()
606 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_bandit()
607 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_bandit()
617 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_uninorth()
618 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_uninorth()
620 	return addr->start == 0xf2000000;  in setup_uninorth()
636 	hose->first_busno = 0xf0;  in setup_u3_agp()
637 	hose->last_busno = 0xff;  in setup_u3_agp()
640 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u3_agp()
641 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u3_agp()
651 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u4_pcie()
652 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u4_pcie()
655 	 * make it visible on bus 0 so that we pick the right type  in setup_u4_pcie()
660 	hose->first_busno = 0x00;  in setup_u4_pcie()
661 	hose->last_busno = 0xff;  in setup_u4_pcie()
673 	for (i = 0; i < 31; i++) {  in parse_region_decode()
674 		if ((decode & (0x80000000 >> i)) == 0)  in parse_region_decode()
677 			base = 0xf0000000 | (((u32)i) << 24);  in parse_region_decode()
678 			end = base + 0x00ffffff;  in parse_region_decode()
681 			end = base + 0x0fffffff;  in parse_region_decode()
692 			hose->mem_offset[cur] = 0;  in parse_region_decode()
693 			DBG("  %d: 0x%08lx-0x%08lx\n", cur, base, end);  in parse_region_decode()
695 			DBG("   :           -0x%08lx\n", end);  in parse_region_decode()
712 	if (of_address_to_resource(np, 0, &cfg_res) ||  in setup_u3_ht()
721 	hose->cfg_data = ioremap(cfg_res.start, 0x02000000);  in setup_u3_ht()
729 	hose->io_base_phys = 0xf4000000;  in setup_u3_ht()
730 	hose->pci_io_size = 0x00400000;  in setup_u3_ht()
732 	hose->io_resource.start = 0;  in setup_u3_ht()
733 	hose->io_resource.end = 0x003fffff;  in setup_u3_ht()
735 	hose->first_busno = 0;  in setup_u3_ht()
736 	hose->last_busno = 0xef;  in setup_u3_ht()
739 	decode = in_be32(hose->cfg_addr + 0x80);  in setup_u3_ht()
741 	DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);  in setup_u3_ht()
744 	 * 0xf8000000 for example is marked as enabled in there while it's  in setup_u3_ht()
748 	 * In a similar vein, region 0xf4000000 is actually the HT IO space but  in setup_u3_ht()
749 	 * also marked as enabled in here and 0xf9000000 is used by some other  in setup_u3_ht()
757 	 * Apple firmware doesn't assign things below 0xfa000000 for that  in setup_u3_ht()
760 	decode &= 0x003fffff;  in setup_u3_ht()
784 	of_address_to_resource(dev, 0, &rsrc);  in pmac_add_bridge()
790 		       " bus 0\n", dev);  in pmac_add_bridge()
796 	hose->first_busno = bus_range ? bus_range[0] : 0;  in pmac_add_bridge()
797 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in pmac_add_bridge()
807 		primary = 0;  in pmac_add_bridge()
815 		primary = 0;  in pmac_add_bridge()
836 		primary = 0;  in pmac_add_bridge()
838 	printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "  in pmac_add_bridge()
844 	DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",  in pmac_add_bridge()
858 	return 0;  in pmac_add_bridge()
887 		return 0;  in pmac_pci_root_bridge_prepare()
895 	PCI_DN(np)->busno = 0xf0;  in pmac_pci_root_bridge_prepare()
897 		PCI_DN(child)->busno = 0xf0;  in pmac_pci_root_bridge_prepare()
899 	return 0;  in pmac_pci_root_bridge_prepare()
920 			if (pmac_add_bridge(np) == 0)  in pmac_pci_init()
934 	if (ht && pmac_add_bridge(ht) != 0)  in pmac_pci_init()
950 		pcibios_assign_bus_offset = 0x10;  in pmac_pci_init()
958 	int updatecfg = 0;  in pmac_pci_enable_device_hook()
987 		pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);  in pmac_pci_enable_device_hook()
988 		pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);  in pmac_pci_enable_device_hook()
993 		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);  in pmac_pci_enable_device_hook()
1027 		dev->resource[0].flags = 0;  in pmac_pci_fixup_ohci()
1043 			pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);  in pmac_pcibios_after_init()
1044 			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);  in pmac_pcibios_after_init()
1050 			pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);  in pmac_pcibios_after_init()
1068 		if (pci_read_config_byte(dev, 0x91, &val) == 0)  in pmac_pci_fixup_cardbus()
1069 			pci_write_config_byte(dev, 0x91, val | 0x30);  in pmac_pci_fixup_cardbus()
1071 		if (pci_read_config_byte(dev, 0x92, &val) == 0)  in pmac_pci_fixup_cardbus()
1072 			pci_write_config_byte(dev, 0x92, val & ~0x06);  in pmac_pci_fixup_cardbus()
1079 		/* 0x8c == TI122X_IRQMUX, 2 says to route the INTA  in pmac_pci_fixup_cardbus()
1081 		if (pci_read_config_byte(dev, 0x8c, &val) == 0)  in pmac_pci_fixup_cardbus()
1082 			pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);  in pmac_pci_fixup_cardbus()
1084 		if (pci_read_config_byte(dev, 0x92, &val) == 0)  in pmac_pci_fixup_cardbus()
1085 			pci_write_config_byte(dev, 0x92, val & ~0x06);  in pmac_pci_fixup_cardbus()
1093        u8 progif = 0;  in pmac_pci_fixup_pciata()
1133 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);  in pmac_pci_fixup_pciata()
1134 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);  in pmac_pci_fixup_pciata()
1135 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);  in pmac_pci_fixup_pciata()
1136 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);  in pmac_pci_fixup_pciata()
1152 	if (PCI_FUNC(dev->devfn) > 0) {  in fixup_k2_sata()
1156 		for (i = 0; i < 6; i++) {  in fixup_k2_sata()
1157 			dev->resource[i].start = dev->resource[i].end = 0;  in fixup_k2_sata()
1158 			dev->resource[i].flags = 0;  in fixup_k2_sata()
1160 					       0);  in fixup_k2_sata()
1166 		for (i = 0; i < 5; i++) {  in fixup_k2_sata()
1167 			dev->resource[i].start = dev->resource[i].end = 0;  in fixup_k2_sata()
1168 			dev->resource[i].flags = 0;  in fixup_k2_sata()
1170 					       0);  in fixup_k2_sata()
1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1190  * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1206 	for (i = 0; i < 3; i++) {  in fixup_u4_pcie()
1210 		/* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they  in fixup_u4_pcie()
1213 		if (r->start >= 0xf0000000 && r->start < 0xf3000000)  in fixup_u4_pcie()
1229 	reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);  in fixup_u4_pcie()
1231 	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);  in fixup_u4_pcie()
1232 	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);  in fixup_u4_pcie()
1233 	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);  in fixup_u4_pcie()