Lines Matching +full:non +full:- +full:continuous
1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
27 * gpio-controller;
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
34 * interrupt-controller;
35 * #interrupt-cells = < 1 >;
78 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
134 /* ---------------------------------------------------------------------
143 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_irq_unmask()
144 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); in mpc52xx_gpt_irq_unmask()
145 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_irq_unmask()
153 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_irq_mask()
154 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); in mpc52xx_gpt_irq_mask()
155 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_irq_mask()
162 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); in mpc52xx_gpt_irq_ack()
171 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type); in mpc52xx_gpt_irq_set_type()
173 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_irq_set_type()
174 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; in mpc52xx_gpt_irq_set_type()
179 out_be32(&gpt->regs->mode, reg); in mpc52xx_gpt_irq_set_type()
180 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_irq_set_type()
198 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK; in mpc52xx_gpt_irq_cascade()
200 generic_handle_domain_irq(gpt->irqhost, 0); in mpc52xx_gpt_irq_cascade()
206 struct mpc52xx_gpt_priv *gpt = h->host_data; in mpc52xx_gpt_irq_map()
208 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); in mpc52xx_gpt_irq_map()
220 struct mpc52xx_gpt_priv *gpt = h->host_data; in mpc52xx_gpt_irq_xlate()
222 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); in mpc52xx_gpt_irq_xlate()
225 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct); in mpc52xx_gpt_irq_xlate()
226 return -EINVAL; in mpc52xx_gpt_irq_xlate()
251 gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt); in mpc52xx_gpt_irq_setup()
252 if (!gpt->irqhost) { in mpc52xx_gpt_irq_setup()
253 dev_err(gpt->dev, "irq_domain_add_linear() failed\n"); in mpc52xx_gpt_irq_setup()
261 * Capture mode. If the mode is non-zero, then the pin could be in mpc52xx_gpt_irq_setup()
263 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_irq_setup()
264 mode = in_be32(&gpt->regs->mode); in mpc52xx_gpt_irq_setup()
266 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC); in mpc52xx_gpt_irq_setup()
267 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_irq_setup()
269 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); in mpc52xx_gpt_irq_setup()
273 /* ---------------------------------------------------------------------
281 return (in_be32(&gpt->regs->status) >> 8) & 1; in mpc52xx_gpt_gpio_get()
291 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v); in mpc52xx_gpt_gpio_set()
294 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_gpio_set()
295 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); in mpc52xx_gpt_gpio_set()
296 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_gpio_set()
304 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); in mpc52xx_gpt_gpio_dir_in()
306 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_gpio_dir_in()
307 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); in mpc52xx_gpt_gpio_dir_in()
308 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_gpio_dir_in()
325 if (!device_property_present(gpt->dev, "gpio-controller")) in mpc52xx_gpt_gpio_setup()
328 gpt->gc.label = kasprintf(GFP_KERNEL, "%pfw", dev_fwnode(gpt->dev)); in mpc52xx_gpt_gpio_setup()
329 if (!gpt->gc.label) { in mpc52xx_gpt_gpio_setup()
330 dev_err(gpt->dev, "out of memory\n"); in mpc52xx_gpt_gpio_setup()
334 gpt->gc.ngpio = 1; in mpc52xx_gpt_gpio_setup()
335 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in; in mpc52xx_gpt_gpio_setup()
336 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out; in mpc52xx_gpt_gpio_setup()
337 gpt->gc.get = mpc52xx_gpt_gpio_get; in mpc52xx_gpt_gpio_setup()
338 gpt->gc.set = mpc52xx_gpt_gpio_set; in mpc52xx_gpt_gpio_setup()
339 gpt->gc.base = -1; in mpc52xx_gpt_gpio_setup()
340 gpt->gc.parent = gpt->dev; in mpc52xx_gpt_gpio_setup()
343 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, in mpc52xx_gpt_gpio_setup()
346 rc = gpiochip_add_data(&gpt->gc, gpt); in mpc52xx_gpt_gpio_setup()
348 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc); in mpc52xx_gpt_gpio_setup()
350 dev_dbg(gpt->dev, "%s() complete.\n", __func__); in mpc52xx_gpt_gpio_setup()
361 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
373 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) { in mpc52xx_gpt_from_irq()
385 int continuous, int as_wdt) in mpc52xx_gpt_do_start() argument
397 } else if (continuous) in mpc52xx_gpt_do_start()
404 clocks = period * (u64)gpt->ipb_freq; in mpc52xx_gpt_do_start()
409 return -EINVAL; in mpc52xx_gpt_do_start()
428 return -EINVAL; in mpc52xx_gpt_do_start()
432 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_do_start()
434 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; in mpc52xx_gpt_do_start()
435 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { in mpc52xx_gpt_do_start()
436 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_do_start()
437 return -EBUSY; in mpc52xx_gpt_do_start()
439 out_be32(&gpt->regs->count, prescale << 16 | clocks); in mpc52xx_gpt_do_start()
440 clrsetbits_be32(&gpt->regs->mode, clear, set); in mpc52xx_gpt_do_start()
441 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_do_start()
447 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
450 * @continuous: set to 1 to make timer continuous free running
455 int continuous) in mpc52xx_gpt_start_timer() argument
457 return mpc52xx_gpt_do_start(gpt, period, continuous, 0); in mpc52xx_gpt_start_timer()
462 * mpc52xx_gpt_stop_timer - Stop a gpt
472 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_stop_timer()
473 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { in mpc52xx_gpt_stop_timer()
474 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_stop_timer()
475 return -EBUSY; in mpc52xx_gpt_stop_timer()
478 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); in mpc52xx_gpt_stop_timer()
479 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_stop_timer()
485 * mpc52xx_gpt_timer_period - Read the timer period
496 raw_spin_lock_irqsave(&gpt->lock, flags); in mpc52xx_gpt_timer_period()
497 period = in_be32(&gpt->regs->count); in mpc52xx_gpt_timer_period()
498 raw_spin_unlock_irqrestore(&gpt->lock, flags); in mpc52xx_gpt_timer_period()
505 do_div(period, gpt->ipb_freq); in mpc52xx_gpt_timer_period()
520 /* wdt-capable gpt */
523 /* low-level wdt functions */
528 raw_spin_lock_irqsave(&gpt_wdt->lock, flags); in mpc52xx_gpt_wdt_ping()
529 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING); in mpc52xx_gpt_wdt_ping()
530 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); in mpc52xx_gpt_wdt_ping()
537 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; in mpc52xx_wdt_write()
550 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; in mpc52xx_wdt_ioctl()
561 ret = -EFAULT; in mpc52xx_wdt_ioctl()
587 * - timeout requested is 1 second; in mpc52xx_wdt_ioctl()
588 * - real timeout @33MHz is 999997090ns in mpc52xx_wdt_ioctl()
589 * - the int divide by 10^9 will return 0. in mpc52xx_wdt_ioctl()
599 ret = -ENOTTY; in mpc52xx_wdt_ioctl()
610 return -ENODEV; in mpc52xx_wdt_open()
614 return -EBUSY; in mpc52xx_wdt_open()
624 file->private_data = mpc52xx_gpt_wdt; in mpc52xx_wdt_open()
630 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */ in mpc52xx_wdt_release()
632 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; in mpc52xx_wdt_release()
635 raw_spin_lock_irqsave(&gpt_wdt->lock, flags); in mpc52xx_wdt_release()
636 clrbits32(&gpt_wdt->regs->mode, in mpc52xx_wdt_release()
638 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; in mpc52xx_wdt_release()
639 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); in mpc52xx_wdt_release()
689 dev_warn(gpt->dev, "starting as wdt failed\n"); in mpc52xx_gpt_wdt_setup()
691 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period); in mpc52xx_gpt_wdt_setup()
710 /* ---------------------------------------------------------------------
717 gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL); in mpc52xx_gpt_probe()
719 return -ENOMEM; in mpc52xx_gpt_probe()
721 raw_spin_lock_init(&gpt->lock); in mpc52xx_gpt_probe()
722 gpt->dev = &ofdev->dev; in mpc52xx_gpt_probe()
723 gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_gpt_probe()
724 gpt->regs = of_iomap(ofdev->dev.of_node, 0); in mpc52xx_gpt_probe()
725 if (!gpt->regs) in mpc52xx_gpt_probe()
726 return -ENOMEM; in mpc52xx_gpt_probe()
728 dev_set_drvdata(&ofdev->dev, gpt); in mpc52xx_gpt_probe()
731 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node); in mpc52xx_gpt_probe()
734 list_add(&gpt->list, &mpc52xx_gpt_list); in mpc52xx_gpt_probe()
738 if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) || in mpc52xx_gpt_probe()
739 of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) { in mpc52xx_gpt_probe()
742 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; in mpc52xx_gpt_probe()
743 on_boot_wdt = of_get_property(ofdev->dev.of_node, in mpc52xx_gpt_probe()
744 "fsl,wdt-on-boot", NULL); in mpc52xx_gpt_probe()
746 dev_info(gpt->dev, "used as watchdog\n"); in mpc52xx_gpt_probe()
747 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; in mpc52xx_gpt_probe()
749 dev_info(gpt->dev, "can function as watchdog\n"); in mpc52xx_gpt_probe()
757 { .compatible = "fsl,mpc5200-gpt", },
760 { .compatible = "fsl,mpc5200-gpt-gpio", },
761 { .compatible = "mpc5200-gpt", },
767 .name = "mpc52xx-gpt",