644 	unsigned int		sdr_base;  member
674 		val = mfdcri(SDR0, port->sdr_base + sdr_offset);  in ppc4xx_pciex_wait_on_sdr()
858 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc440spe_pciex_init_port_hw()
859 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);  in ppc440spe_pciex_init_port_hw()
861 		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);  in ppc440spe_pciex_init_port_hw()
862 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
863 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
864 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
865 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
867 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,  in ppc440spe_pciex_init_port_hw()
869 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,  in ppc440spe_pciex_init_port_hw()
871 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,  in ppc440spe_pciex_init_port_hw()
873 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,  in ppc440spe_pciex_init_port_hw()
876 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc440spe_pciex_init_port_hw()
966 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc460ex_pciex_init_port_hw()
967 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);  in ppc460ex_pciex_init_port_hw()
968 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);  in ppc460ex_pciex_init_port_hw()
997 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
998 	       mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |  in ppc460ex_pciex_init_port_hw()
1014 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
1015 	       (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &  in ppc460ex_pciex_init_port_hw()
1081 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in apm821xx_pciex_init_port_hw()
1082 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in apm821xx_pciex_init_port_hw()
1083 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in apm821xx_pciex_init_port_hw()
1093 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1094 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |  in apm821xx_pciex_init_port_hw()
1098 	val = PESDR0_460EX_RSTSTA - port->sdr_base;  in apm821xx_pciex_init_port_hw()
1103 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1104 			(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &  in apm821xx_pciex_init_port_hw()
1211 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,  in ppc460sx_pciex_init_port_hw()
1214 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,  in ppc460sx_pciex_init_port_hw()
1217 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460sx_pciex_init_port_hw()
1280 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);  in ppc405ex_pcie_phy_reset()
1285 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);  in ppc405ex_pcie_phy_reset()
1287 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);  in ppc405ex_pcie_phy_reset()
1291 	while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))  in ppc405ex_pcie_phy_reset()
1295 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);  in ppc405ex_pcie_phy_reset()
1307 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,  in ppc405ex_pciex_init_port_hw()
1310 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in ppc405ex_pciex_init_port_hw()
1311 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in ppc405ex_pciex_init_port_hw()
1312 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);  in ppc405ex_pciex_init_port_hw()
1313 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);  in ppc405ex_pciex_init_port_hw()
1322 	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);  in ppc405ex_pciex_init_port_hw()
1523 	if (port->sdr_base) {  in ppc4xx_pciex_port_init()
1541 		dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);  in ppc4xx_pciex_port_init()
2120 		port->sdr_base = *pval;  in ppc4xx_probe_pciex_bridge()