Lines Matching +full:0 +full:x80800000
40 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) in ppc440spe_revA()
54 return 0; in ppc440spe_revA()
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { in fixup_ppc4xx_pci_bridge()
83 dev->resource[i].start = dev->resource[i].end = 0; in fixup_ppc4xx_pci_bridge()
84 dev->resource[i].flags = 0; in fixup_ppc4xx_pci_bridge()
103 res->start = 0; in ppc4xx_parse_dma_ranges()
104 size = 0x80000000; in ppc4xx_parse_dma_ranges()
114 while ((rlen -= np * 4) >= 0) { in ppc4xx_parse_dma_ranges()
115 u32 pci_space = ranges[0]; in ppc4xx_parse_dma_ranges()
120 if (cpu_addr == OF_BAD_ADDR || size == 0) in ppc4xx_parse_dma_ranges()
124 if ((pci_space & 0x03000000) != 0x02000000) in ppc4xx_parse_dma_ranges()
127 /* We currently only support memory at 0, and pci_addr in ppc4xx_parse_dma_ranges()
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) { in ppc4xx_parse_dma_ranges()
132 " 0x%016llx...0x%016llx -> 0x%016llx\n", in ppc4xx_parse_dma_ranges()
139 if (!(pci_space & 0x40000000)) in ppc4xx_parse_dma_ranges()
147 (pci_addr + size) > 0x100000000ull) in ppc4xx_parse_dma_ranges()
148 res->end = 0xffffffff; in ppc4xx_parse_dma_ranges()
171 if ((size & (size - 1)) != 0 || in ppc4xx_parse_dma_ranges()
172 (res->start & (size - 1)) != 0) { in ppc4xx_parse_dma_ranges()
180 if (res->end > 0xffffffff && in ppc4xx_parse_dma_ranges()
193 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", in ppc4xx_parse_dma_ranges()
195 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n", in ppc4xx_parse_dma_ranges()
197 printk(KERN_INFO "DMA window size 0x%016llx\n", in ppc4xx_parse_dma_ranges()
199 return 0; in ppc4xx_parse_dma_ranges()
219 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. in ppc4xx_setup_one_pci_PMM()
227 plb_addr &= 0xffffffffull; in ppc4xx_setup_one_pci_PMM()
233 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || in ppc4xx_setup_one_pci_PMM()
234 size < 0x1000 || (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pci_PMM()
238 ma = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_setup_one_pci_PMM()
245 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
246 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
247 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
248 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
250 return 0; in ppc4xx_setup_one_pci_PMM()
256 int i, j, found_isa_hole = 0; in ppc4xx_configure_pci_PMMs()
259 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pci_PMMs()
277 j) == 0) { in ppc4xx_configure_pci_PMMs()
280 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pci_PMMs()
290 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pci_PMMs()
291 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pci_PMMs()
304 sa = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_configure_pci_PTMs()
305 sa |= 0x1; in ppc4xx_configure_pci_PTMs()
307 /* RAM is always at 0 local for now */ in ppc4xx_configure_pci_PTMs()
308 writel(0, reg + PCIL0_PTM1LA); in ppc4xx_configure_pci_PTMs()
312 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
314 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
315 PCI_BASE_ADDRESS_2, 0x00000000); in ppc4xx_configure_pci_PTMs()
316 early_write_config_word(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
317 PCI_COMMAND, 0x0006); in ppc4xx_configure_pci_PTMs()
329 int primary = 0; in ppc4xx_probe_pci_bridge()
338 if (of_address_to_resource(np, 0, &rsrc_cfg)) { in ppc4xx_probe_pci_bridge()
369 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pci_bridge()
370 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pci_bridge()
373 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); in ppc4xx_probe_pci_bridge()
376 writel(0, reg + PCIL0_PMM0MA); in ppc4xx_probe_pci_bridge()
377 writel(0, reg + PCIL0_PMM1MA); in ppc4xx_probe_pci_bridge()
378 writel(0, reg + PCIL0_PMM2MA); in ppc4xx_probe_pci_bridge()
379 writel(0, reg + PCIL0_PTM1MS); in ppc4xx_probe_pci_bridge()
380 writel(0, reg + PCIL0_PTM2MS); in ppc4xx_probe_pci_bridge()
386 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) in ppc4xx_probe_pci_bridge()
420 if (!is_power_of_2(size) || size < 0x1000 || in ppc4xx_setup_one_pcix_POM()
421 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pcix_POM()
432 sa = (0xffffffffu << ilog2(size)) | 0x1; in ppc4xx_setup_one_pcix_POM()
435 if (index == 0) { in ppc4xx_setup_one_pcix_POM()
449 return 0; in ppc4xx_setup_one_pcix_POM()
455 int i, j, found_isa_hole = 0; in ppc4xx_configure_pcix_POMs()
458 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pcix_POMs()
476 j) == 0) { in ppc4xx_configure_pcix_POMs()
479 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pcix_POMs()
489 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pcix_POMs()
490 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pcix_POMs()
504 /* RAM is always at 0 */ in ppc4xx_configure_pcix_PIMs()
505 writel(0x00000000, reg + PCIX0_PIM0LAH); in ppc4xx_configure_pcix_PIMs()
506 writel(0x00000000, reg + PCIX0_PIM0LAL); in ppc4xx_configure_pcix_PIMs()
509 sa = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_configure_pcix_PIMs()
510 sa |= 0x1; in ppc4xx_configure_pcix_PIMs()
512 sa |= 0x2; in ppc4xx_configure_pcix_PIMs()
514 sa |= 0x4; in ppc4xx_configure_pcix_PIMs()
517 writel(0xffffffff, reg + PCIX0_PIM0SAH); in ppc4xx_configure_pcix_PIMs()
520 writel(0x00000000, reg + PCIX0_BAR0H); in ppc4xx_configure_pcix_PIMs()
522 writew(0x0006, reg + PCIX0_COMMAND); in ppc4xx_configure_pcix_PIMs()
533 int big_pim = 0, msi = 0, primary = 0; in ppc4xx_probe_pcix_bridge()
536 if (of_address_to_resource(np, 0, &rsrc_cfg)) { in ppc4xx_probe_pcix_bridge()
575 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pcix_bridge()
576 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pcix_bridge()
579 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, in ppc4xx_probe_pcix_bridge()
583 writel(0, reg + PCIX0_POM0SA); in ppc4xx_probe_pcix_bridge()
584 writel(0, reg + PCIX0_POM1SA); in ppc4xx_probe_pcix_bridge()
585 writel(0, reg + PCIX0_POM2SA); in ppc4xx_probe_pcix_bridge()
586 writel(0, reg + PCIX0_PIM0SA); in ppc4xx_probe_pcix_bridge()
587 writel(0, reg + PCIX0_PIM1SA); in ppc4xx_probe_pcix_bridge()
588 writel(0, reg + PCIX0_PIM2SA); in ppc4xx_probe_pcix_bridge()
590 writel(0, reg + PCIX0_PIM0SAH); in ppc4xx_probe_pcix_bridge()
591 writel(0, reg + PCIX0_PIM2SAH); in ppc4xx_probe_pcix_bridge()
598 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) in ppc4xx_probe_pcix_bridge()
634 #define MAX_PCIE_BUS_MAPPED 0x40
678 return 0; in ppc4xx_pciex_wait_on_sdr()
688 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { in ppc4xx_pciex_port_reset_sdr()
693 return 0; in ppc4xx_pciex_port_reset_sdr()
715 0x1000, 0x1000, 2000)) in ppc4xx_pciex_check_link_sdr()
733 int err = 0; in ppc440spe_pciex_check_reset()
736 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { in ppc440spe_pciex_check_reset()
744 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
745 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
746 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
754 if (!(valPE0 & 0x01000000) || in ppc440spe_pciex_check_reset()
755 !(valPE1 & 0x01000000) || in ppc440spe_pciex_check_reset()
756 !(valPE2 & 0x01000000)) { in ppc440spe_pciex_check_reset()
762 if (!(valPE0 & 0x00010000) || in ppc440spe_pciex_check_reset()
763 !(valPE1 & 0x00010000) || in ppc440spe_pciex_check_reset()
764 !(valPE2 & 0x00010000)) { in ppc440spe_pciex_check_reset()
770 if ((valPE0 & 0x00001000) || in ppc440spe_pciex_check_reset()
771 (valPE1 & 0x00001000) || in ppc440spe_pciex_check_reset()
772 (valPE2 & 0x00001000)) { in ppc440spe_pciex_check_reset()
778 if ((valPE0 & 0x10000000) || in ppc440spe_pciex_check_reset()
779 (valPE1 & 0x10000000) || in ppc440spe_pciex_check_reset()
780 (valPE2 & 0x10000000)) { in ppc440spe_pciex_check_reset()
786 if ((valPE0 & 0x00100000) || in ppc440spe_pciex_check_reset()
787 (valPE1 & 0x00100000) || in ppc440spe_pciex_check_reset()
788 (valPE2 & 0x00100000)) { in ppc440spe_pciex_check_reset()
794 if ((valPE0 & 0x00000100) || in ppc440spe_pciex_check_reset()
795 (valPE1 & 0x00000100) || in ppc440spe_pciex_check_reset()
796 (valPE2 & 0x00000100)) { in ppc440spe_pciex_check_reset()
810 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); in ppc440spe_pciex_core_init()
816 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { in ppc440spe_pciex_core_init()
818 "failed (0x%08x)\n", in ppc440spe_pciex_core_init()
824 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); in ppc440spe_pciex_core_init()
828 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { in ppc440spe_pciex_core_init()
853 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
859 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
865 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
866 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
868 0x35000000); in ppc440spe_pciex_init_port_hw()
870 0x35000000); in ppc440spe_pciex_init_port_hw()
872 0x35000000); in ppc440spe_pciex_init_port_hw()
874 0x35000000); in ppc440spe_pciex_init_port_hw()
899 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
904 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
905 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
906 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
907 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
908 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
909 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
910 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
911 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
913 return 0; in ppc440speA_pciex_init_utl()
919 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
921 return 0; in ppc440speB_pciex_init_utl()
958 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
960 utlset1 = 0x20000000; in ppc460ex_pciex_init_port_hw()
963 utlset1 = 0x20101101; in ppc460ex_pciex_init_port_hw()
968 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
971 case 0: in ppc460ex_pciex_init_port_hw()
972 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
973 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
974 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
976 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
980 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
981 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
982 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
983 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
984 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
985 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
986 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
987 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
988 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
989 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
990 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
991 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
993 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
1004 case 0: in ppc460ex_pciex_init_port_hw()
1005 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) in ppc460ex_pciex_init_port_hw()
1009 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) in ppc460ex_pciex_init_port_hw()
1026 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1031 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1032 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1033 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1034 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1035 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1036 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1037 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1038 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1039 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1041 return 0; in ppc460ex_pciex_init_utl()
1071 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); in apm821xx_pciex_init_port_hw()
1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1083 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1085 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in apm821xx_pciex_init_port_hw()
1086 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in apm821xx_pciex_init_port_hw()
1087 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in apm821xx_pciex_init_port_hw()
1089 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); in apm821xx_pciex_init_port_hw()
1091 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); in apm821xx_pciex_init_port_hw()
1099 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) { in apm821xx_pciex_init_port_hw()
1109 return 0; in apm821xx_pciex_init_port_hw()
1124 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1125 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1126 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1127 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1128 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1129 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1130 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1131 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1133 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1134 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1135 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1136 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1138 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1139 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1140 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1141 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1144 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1145 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1146 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1147 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1148 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1149 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1150 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1151 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1153 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1154 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1155 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1156 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1158 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1159 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1160 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1161 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1164 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); in ppc460sx_pciex_core_init()
1165 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1166 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1169 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); in ppc460sx_pciex_core_init()
1170 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1171 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1174 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1175 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1180 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); in ppc460sx_pciex_core_init()
1196 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == in ppc460sx_pciex_core_init()
1197 0x00000001)) { in ppc460sx_pciex_core_init()
1212 0x01000000, 0); in ppc460sx_pciex_init_port_hw()
1215 0, 0x01000000); in ppc460sx_pciex_init_port_hw()
1229 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1231 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1232 return 0; in ppc460sx_pciex_init_utl()
1240 port->link = 0; in ppc460sx_pciex_check_link()
1242 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1249 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA) in ppc460sx_pciex_check_link()
1280 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); in ppc405ex_pcie_phy_reset()
1285 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); in ppc405ex_pcie_phy_reset()
1287 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); in ppc405ex_pcie_phy_reset()
1291 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) in ppc405ex_pcie_phy_reset()
1295 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); in ppc405ex_pcie_phy_reset()
1310 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in ppc405ex_pciex_init_port_hw()
1311 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in ppc405ex_pciex_init_port_hw()
1312 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); in ppc405ex_pciex_init_port_hw()
1313 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); in ppc405ex_pciex_init_port_hw()
1323 if (!(val & 0x00001000)) in ppc405ex_pciex_init_port_hw()
1326 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ in ppc405ex_pciex_init_port_hw()
1335 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc405ex_pciex_init_utl()
1340 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); in ppc405ex_pciex_init_utl()
1341 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc405ex_pciex_init_utl()
1342 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1343 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); in ppc405ex_pciex_init_utl()
1344 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc405ex_pciex_init_utl()
1345 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1346 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc405ex_pciex_init_utl()
1347 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc405ex_pciex_init_utl()
1349 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc405ex_pciex_init_utl()
1351 return 0; in ppc405ex_pciex_init_utl()
1374 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT); in ppc_476fpe_pciex_check_link()
1375 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1376 0x1000); in ppc_476fpe_pciex_check_link()
1417 return 0; in ppc4xx_pciex_check_core_init()
1448 if (count > 0) { in ppc4xx_pciex_check_core_init()
1454 return 0; in ppc4xx_pciex_check_core_init()
1471 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1480 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1483 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1484 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1485 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1486 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1491 int rc = 0; in ppc4xx_pciex_port_init()
1496 if (rc != 0) in ppc4xx_pciex_port_init()
1511 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1531 port->link = 0; in ppc4xx_pciex_port_init()
1538 port->link = 0; in ppc4xx_pciex_port_init()
1541 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1546 return 0; in ppc4xx_pciex_port_init()
1570 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1575 PCI_SLOT(devfn) != 0) in ppc4xx_pciex_validate_bdf()
1582 return 0; in ppc4xx_pciex_validate_bdf()
1613 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_read_config()
1627 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1641 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_read_config()
1642 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", in ppc4xx_pciex_read_config()
1647 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1649 if (len != 4 || offset != 0) in ppc4xx_pciex_read_config()
1651 *val = 0xffff0001; in ppc4xx_pciex_read_config()
1668 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_write_config()
1681 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_write_config()
1682 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", in ppc4xx_pciex_write_config()
1721 (index < 2 && size < 0x100000) || in ppc4xx_setup_one_pciex_POM()
1722 (index == 2 && size < 0x100) || in ppc4xx_setup_one_pciex_POM()
1723 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pciex_POM()
1733 sa = (0xffffffffu << ilog2(size)) | 0x1; in ppc4xx_setup_one_pciex_POM()
1737 case 0: in ppc4xx_setup_one_pciex_POM()
1742 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1774 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1782 return 0; in ppc4xx_setup_one_pciex_POM()
1789 int i, j, found_isa_hole = 0; in ppc4xx_configure_pciex_POMs()
1792 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pciex_POMs()
1811 j) == 0) { in ppc4xx_configure_pciex_POMs()
1814 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pciex_POMs()
1825 hose->isa_mem_phys, 0, in ppc4xx_configure_pciex_POMs()
1826 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pciex_POMs()
1830 /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! in ppc4xx_configure_pciex_POMs()
1835 hose->io_base_phys, 0, in ppc4xx_configure_pciex_POMs()
1836 0x10000, IORESOURCE_IO, 2); in ppc4xx_configure_pciex_POMs()
1848 resource_size_t ep_addr = 0; in ppc4xx_configure_pciex_PIMs()
1852 * 0 (SDRAM). This should probably be configurable via a dts in ppc4xx_configure_pciex_PIMs()
1857 sa = (0xffffffffffffffffull << ilog2(ep_size)); in ppc4xx_configure_pciex_PIMs()
1865 out_le32(mbase + PECFG_BAR1MPA, 0); in ppc4xx_configure_pciex_PIMs()
1866 out_le32(mbase + PECFG_BAR2HMPA, 0); in ppc4xx_configure_pciex_PIMs()
1867 out_le32(mbase + PECFG_BAR2LMPA, 0); in ppc4xx_configure_pciex_PIMs()
1876 sa = (0xffffffffffffffffull << ilog2(size)); in ppc4xx_configure_pciex_PIMs()
1893 out_le32(mbase + PECFG_PIM0LAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1894 out_le32(mbase + PECFG_PIM0LAH, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1895 out_le32(mbase + PECFG_PIM1LAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1896 out_le32(mbase + PECFG_PIM1LAH, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1897 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); in ppc4xx_configure_pciex_PIMs()
1898 out_le32(mbase + PECFG_PIM01SAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1905 out_le32(mbase + PECFG_PIMEN, 0x1); in ppc4xx_configure_pciex_PIMs()
1918 int primary = 0, busses; in ppc4xx_pciex_port_setup_hose()
1941 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_pciex_port_setup_hose()
1942 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_pciex_port_setup_hose()
1960 (hose->first_busno + 1) * 0x100000, in ppc4xx_pciex_port_setup_hose()
1961 busses * 0x100000); in ppc4xx_pciex_port_setup_hose()
1973 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1983 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", in ppc4xx_pciex_port_setup_hose()
2003 out_le32(mbase + PECFG_PIMEN, 0); in ppc4xx_pciex_port_setup_hose()
2009 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) in ppc4xx_pciex_port_setup_hose()
2031 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
2033 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
2035 out_le16(mbase + 0x200, val); in ppc4xx_pciex_port_setup_hose()
2042 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2044 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2046 out_le16(mbase + 0x202, val); in ppc4xx_pciex_port_setup_hose()
2050 out_le16(mbase + 0x204, 0x7); in ppc4xx_pciex_port_setup_hose()
2054 out_le32(mbase + 0x208, 0x06040001); in ppc4xx_pciex_port_setup_hose()
2060 out_le32(mbase + 0x208, 0x0b200001); in ppc4xx_pciex_port_setup_hose()
2130 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2138 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2149 dcrs = dcr_resource_start(np, 0); in ppc4xx_probe_pciex_bridge()
2150 if (dcrs == 0) { in ppc4xx_probe_pciex_bridge()
2154 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2183 return 0; in ppc4xx_pci_find_bridges()