Lines Matching +full:4 +full:c
23 #define PM_BYTE_SH 4 /* Byte number of event bus to use */
32 #define PM_IFU 4
112 * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
133 (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
134 (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
135 (1<<3) | (1<<4) | (1<<5),
137 (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
138 (1<<4) /* PMC8: PM_MRK_LSU_FIN */
156 bit = (pmc <= 4)? pmc - 1: 8 - pmc; in p970_marked_instr_event()
158 bit = 4; in p970_marked_instr_event()
172 /* byte 2 bits 0,2,3,4,6; all of byte 1 */ in p970_marked_instr_event()
176 mask = 0x50 << 24; /* byte 3 bits 4,6 */ in p970_marked_instr_event()
217 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8. in p970_get_constraint()
222 mask |= 0xfULL << (28 - 4 * byte); in p970_get_constraint()
223 value |= (unsigned long)unit << (28 - 4 * byte); in p970_get_constraint()
230 /* increment PMC3/4/7/8 field */ in p970_get_constraint()
267 unsigned char busbyte[4]; in p970_compute_mmcr()
269 unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 }; in p970_compute_mmcr()
288 /* count 1/2/5/6 vs 3/4/7/8 use */ in p970_compute_mmcr()
304 if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4) in p970_compute_mmcr()
315 unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */ in p970_compute_mmcr()
323 mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH; in p970_compute_mmcr()
330 for (byte = 0; byte < 4; ++byte) { in p970_compute_mmcr()
367 } else if (pmc_grp_use[grp] < 4) { in p970_compute_mmcr()
431 #define C(x) PERF_COUNT_HW_CACHE_##x macro
438 static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
439 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
440 [C(OP_READ)] = { 0x8810, 0x3810 },
441 [C(OP_WRITE)] = { 0x7810, 0x813 },
442 [C(OP_PREFETCH)] = { 0x731, 0 },
444 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
445 [C(OP_READ)] = { 0, 0 },
446 [C(OP_WRITE)] = { -1, -1 },
447 [C(OP_PREFETCH)] = { 0, 0 },
449 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
450 [C(OP_READ)] = { 0, 0 },
451 [C(OP_WRITE)] = { 0, 0 },
452 [C(OP_PREFETCH)] = { 0x733, 0 },
454 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
455 [C(OP_READ)] = { 0, 0x704 },
456 [C(OP_WRITE)] = { -1, -1 },
457 [C(OP_PREFETCH)] = { -1, -1 },
459 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
460 [C(OP_READ)] = { 0, 0x700 },
461 [C(OP_WRITE)] = { -1, -1 },
462 [C(OP_PREFETCH)] = { -1, -1 },
464 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
465 [C(OP_READ)] = { 0x431, 0x327 },
466 [C(OP_WRITE)] = { -1, -1 },
467 [C(OP_PREFETCH)] = { -1, -1 },
469 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
470 [C(OP_READ)] = { -1, -1 },
471 [C(OP_WRITE)] = { -1, -1 },
472 [C(OP_PREFETCH)] = { -1, -1 },