1 /* SPDX-License-Identifier: GPL-2.0-or-later */
38 #define EVENT_PMC_SHIFT		16	/* PMC number (1-based) */
42 #define EVENT_COMBINE_SHIFT	11	/* Combine bit */
44 #define EVENT_COMBINE(v)	(((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)  argument
45 #define EVENT_MARKED_SHIFT	8	/* Marked bit */
73 #define p9_EVENT_COMBINE_SHIFT	10	/* Combine bit */
75 #define p9_EVENT_COMBINE(v)	(((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)  argument
78 #define p9_SDAR_MODE(v)		(((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)  argument
95 #define p10_SDAR_MODE(v)		(((v) >> p10_SDAR_MODE_SHIFT) & \  argument
108 /* Event Threshold Compare bit constant for power10 in config1 attribute */
129  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
132  *                           [  thresh_cmp bits for p10]           thresh_sel -*
135  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
138  *      BHRB IFM -*  |    |  |*radix_scope      |      Count of events for each PMC.
139  *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
140  *      L1 I/D qualifier -*                     |
141  *                     nc - number of counters -*
144  * we want the low bit of each field to be added to any existing value.
149 #define CNST_FAB_MATCH_VAL(v)	(((v) & EVENT_THR_CTL_MASK) << 56)  argument
153 #define CNST_THRESH_VAL(v)	(((v) & EVENT_THRESH_MASK) << 32)  argument
156 #define CNST_THRESH_CTL_SEL_VAL(v)	(((v) & 0x7ffull) << 32)  argument
159 #define p10_CNST_THRESH_CMP_VAL(v) (((v) & 0x7ffull) << 43)  argument
162 #define CNST_EBB_VAL(v)		(((v) & EVENT_EBB_MASK) << 24)  argument
165 #define CNST_IFM_VAL(v)		(((v) & EVENT_IFM_MASK) << 25)  argument
168 #define CNST_L1_QUAL_VAL(v)	(((v) & 3) << 22)  argument
171 #define CNST_SAMPLE_VAL(v)	(((v) & EVENT_SAMPLE_MASK) << 16)  argument
174 #define CNST_CACHE_GROUP_VAL(v)	(((v) & 0xffull) << 55)  argument
179 #define CNST_L2L3_GROUP_VAL(v)	(((v) & 0x1full) << 55)  argument
182 #define CNST_RADIX_SCOPE_GROUP_VAL(v)	(((v) & 0x1ull) << 21)  argument
187  * the fifth event to overflow and set the 4th bit. To achieve that we bias the
196  * For the per-PMC fields we have two bits. The low bit is added, so if two
197  * events ask for the same PMC the sum will overflow, setting the high bit,
198  * indicating an error. So our mask sets the high bit.
200 #define CNST_PMC_SHIFT(pmc)	((pmc - 1) * 2)
210 #define MMCR1_UNIT_SHIFT(pmc)		(60 - (4 * ((pmc) - 1)))
211 #define MMCR1_COMBINE_SHIFT(pmc)	(35 - ((pmc) - 1))
212 #define MMCR1_PMCSEL_SHIFT(pmc)		(24 - (((pmc) - 1)) * 8)
218 #define p9_MMCR1_COMBINE_SHIFT(pmc)	(38 - ((pmc - 1) * 2))
234 #define MMCRA_THR_CTR_MANT(v)		(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\  argument
239 #define MMCRA_THR_CTR_EXP(v)		(((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\  argument
243 #define P10_MMCRA_THR_CTR_MANT(v)	(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\  argument
246 /* MMCRA Threshold Compare bit constant for power9 */
250 #define MMCR2_FCS(pmc)			(1ull << (63 - (((pmc) - 1) * 9)))
251 #define MMCR2_FCP(pmc)			(1ull << (62 - (((pmc) - 1) * 9)))
252 #define MMCR2_FCWAIT(pmc)		(1ull << (58 - (((pmc) - 1) * 9)))
253 #define MMCR2_FCH(pmc)			(1ull << (57 - (((pmc) - 1) * 9)))
259 #define MMCR3_SHIFT(pmc)		(49 - (15 * ((pmc) - 1)))
271 #define P10_SIER2_FINISH_CYC(sier2)	(((sier2) >> (63 - 37)) & 0x7fful)
272 #define P10_SIER2_DISPATCH_CYC(sier2)	(((sier2) >> (63 - 13)) & 0x7fful)