Lines Matching full:need
91 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
109 * MAS1 is preset for all we need except for TID that needs to
181 * - TSIZE need change if !base page size, not
183 * MAS 2 : Defaults not useful, need to be redone
219 /* We need to check if it was an instruction miss */
253 * No HES or NV hint on TLB1, so we need to do software round-robin
254 * No tlbsrx. so we need a spinlock, and we have to deal
379 /* Now, we need to walk the page tables. First check if we are in
414 * MAS 2 : Default not 2M-aligned, need to be redone
464 * MAS 1 : Need to clear IND and set TSIZE
504 /* We need to check if it was an instruction miss */
549 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
571 * MAS1 is preset for all we need except for TID that needs to
593 /* If we take a recursive fault, the second level handler may need
680 * - TSIZE need change if !base page size, not
682 * MAS 2 : Defaults not useful, need to be redone
727 /* We need to check if it was an instruction miss */
775 /* If kernel, we need to clear MAS1 TID */
792 /* Now, we need to walk the page tables. First check if we are in
853 /* If we fault here, things are a little bit tricky. We need to call
854 * either data or instruction store fault, and we need to retrieve
862 * However, we do need to double check that, because we may just hit
868 * level as well. Since we are doing that, we don't need to clear or
944 /* If we take a recursive fault, the second level handler may need
1011 /* Now, we need to walk the page tables. First check if we are in
1046 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
1049 * 4K page we need to extract a bit from the virtual address and
1079 /* We need to check if it was an instruction miss. We know this
1107 * We also need to be careful about MAS registers here & TLB reservation,
1128 /* MAS1 need whole new setup. */