Lines Matching +full:1 +full:- +full:v0
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 /* 0 == don't use VMX, 1 == use VMX */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
136 6: bf cr7*4+1,7f
178 9: clrldi r5,r5,(64-4)
191 12: bf cr7*4+1,13f
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
240 ble 1f
242 1: lis r0,0x0E00 /* depth=7 */
245 ori r10,r7,1 /* stream=1 */
247 lis r8,0x8000 /* GO=1 */
264 rldicl. r6,r6,0,(64-4)
270 clrldi r6,r6,(64-4)
272 bf cr7*4+3,1f
274 addi r4,r4,1
276 addi r3,r3,1
278 1: bf cr7*4+2,2f
284 2: bf cr7*4+1,3f
302 clrldi r6,r6,(64-7)
316 lvx v0,r4,r9
319 stvx v0,r3,r9
322 6: bf cr7*4+1,7f
326 lvx v0,r4,r11
331 stvx v0,r3,r11
361 lvx v0,r4,r16
370 stvx v0,r3,r16
379 clrldi r5,r5,(64-7)
383 bf cr7*4+1,9f
387 lvx v0,r4,r11
392 stvx v0,r3,r11
397 lvx v0,r4,r9
400 stvx v0,r3,r9
410 11: clrldi r5,r5,(64-4)
418 12: bf cr7*4+1,13f
435 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
442 clrldi r6,r6,(64-4)
444 bf cr7*4+3,1f
446 addi r4,r4,1
448 addi r3,r3,1
450 1: bf cr7*4+2,2f
456 2: bf cr7*4+1,3f
476 clrldi r6,r6,(64-7)
483 lvx v0,0,r4
488 VPERM(v8,v0,v1,v16)
492 vor v0,v1,v1
496 VPERM(v8,v0,v1,v16)
497 lvx v0,r4,r9
498 VPERM(v9,v1,v0,v16)
504 6: bf cr7*4+1,7f
506 VPERM(v8,v0,v3,v16)
511 lvx v0,r4,r11
512 VPERM(v11,v1,v0,v16)
541 VPERM(v8,v0,v7,v16)
554 lvx v0,r4,r16
555 VPERM(v15,v1,v0,v16)
573 clrldi r5,r5,(64-7)
577 bf cr7*4+1,9f
579 VPERM(v8,v0,v3,v16)
584 lvx v0,r4,r11
585 VPERM(v11,v1,v0,v16)
595 VPERM(v8,v0,v1,v16)
596 lvx v0,r4,r9
597 VPERM(v9,v1,v0,v16)
605 VPERM(v8,v0,v1,v16)
611 11: clrldi r5,r5,(64-4)
612 addi r4,r4,-16 /* Unwind the +16 load offset */
622 12: bf cr7*4+1,13f
639 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)