Lines Matching full:std
71 std r0, PPC_LR_STKOFF(r1)
74 std r10, HSTATE_HOST_MSR(r13)
268 std r5, 8(r1) // Save CR in caller's frame
269 std r0, 16(r1) // Save LR in caller's frame
275 std r3, 32(r1) // Save SRR1 wakeup value
329 std r0, 32(r1)
333 std r6, HSTATE_DSCR(r13)
361 std r0, HSTATE_KVM_VCPU(r13)
369 std r0, HSTATE_KVM_VCORE(r13)
517 std r0, PPC_LR_STKOFF(r1)
521 std r1, HSTATE_HOST_R1(r13)
580 std r8, VCORE_TB_OFFSET_APPL(r5)
636 std r5,HSTATE_PURR(r13)
637 std r6,HSTATE_SPURR(r13)
649 std r5, STACK_SLOT_CIABR(r1)
650 std r6, STACK_SLOT_DAWR0(r1)
651 std r7, STACK_SLOT_DAWRX0(r1)
652 std r8, STACK_SLOT_IAMR(r1)
654 std r5, STACK_SLOT_FSCR(r1)
658 std r5, STACK_SLOT_AMR(r1)
660 std r6, STACK_SLOT_UAMOR(r1)
998 std r0, VCPU_GPR(R0)(r9)
999 std r1, VCPU_GPR(R1)(r9)
1000 std r2, VCPU_GPR(R2)(r9)
1001 std r3, VCPU_GPR(R3)(r9)
1002 std r4, VCPU_GPR(R4)(r9)
1003 std r5, VCPU_GPR(R5)(r9)
1004 std r6, VCPU_GPR(R6)(r9)
1005 std r7, VCPU_GPR(R7)(r9)
1006 std r8, VCPU_GPR(R8)(r9)
1008 std r0, VCPU_GPR(R9)(r9)
1009 std r10, VCPU_GPR(R10)(r9)
1010 std r11, VCPU_GPR(R11)(r9)
1012 std r3, VCPU_GPR(R12)(r9)
1015 std r4, VCPU_CR(r9)
1018 std r3, VCPU_CFAR(r9)
1022 std r4, VCPU_PPR(r9)
1031 std r10, VCPU_SRR0(r9)
1032 std r11, VCPU_SRR1(r9)
1040 1: std r10, VCPU_PC(r9)
1041 std r11, VCPU_MSR(r9)
1045 std r3, VCPU_GPR(R13)(r9)
1046 std r4, VCPU_LR(r9)
1081 std r3, VCPU_CTR(r9)
1082 std r4, VCPU_XER(r9)
1087 std r3, VCPU_DAR(r9)
1093 std r3, VCPU_FAULT_DAR(r9)
1123 std r3, VCPU_HFSCR(r9)
1162 std r8,VCPU_SLB_E(r7)
1163 std r3,VCPU_SLB_V(r7)
1199 std r5,VCPU_DEC_EXPIRES(r9)
1227 std r5,VCPU_PURR(r9)
1228 std r6,VCPU_SPURR(r9)
1250 std r5, VCPU_IAMR(r9)
1252 std r7, VCPU_FSCR(r9)
1255 std r5, VCPU_IC(r9)
1256 std r7, VCPU_TAR(r9)
1258 std r8, VCPU_EBBHR(r9)
1263 std r5, VCPU_EBBRR(r9)
1264 std r6, VCPU_BESCR(r9)
1266 std r8, VCPU_WORT(r9)
1271 std r5, VCPU_TCSCR(r9)
1272 std r6, VCPU_ACOP(r9)
1273 std r7, VCPU_CSIGR(r9)
1274 std r8, VCPU_TACR(r9)
1299 std r5,VCPU_AMR(r9)
1300 std r6,VCPU_UAMOR(r9)
1309 std r8, VCPU_DSCR(r9)
1313 std r14, VCPU_GPR(R14)(r9)
1314 std r15, VCPU_GPR(R15)(r9)
1315 std r16, VCPU_GPR(R16)(r9)
1316 std r17, VCPU_GPR(R17)(r9)
1317 std r18, VCPU_GPR(R18)(r9)
1318 std r19, VCPU_GPR(R19)(r9)
1319 std r20, VCPU_GPR(R20)(r9)
1320 std r21, VCPU_GPR(R21)(r9)
1321 std r22, VCPU_GPR(R22)(r9)
1322 std r23, VCPU_GPR(R23)(r9)
1323 std r24, VCPU_GPR(R24)(r9)
1324 std r25, VCPU_GPR(R25)(r9)
1325 std r26, VCPU_GPR(R26)(r9)
1326 std r27, VCPU_GPR(R27)(r9)
1327 std r28, VCPU_GPR(R28)(r9)
1328 std r29, VCPU_GPR(R29)(r9)
1329 std r30, VCPU_GPR(R30)(r9)
1330 std r31, VCPU_GPR(R31)(r9)
1337 std r3, VCPU_SPRG0(r9)
1338 std r4, VCPU_SPRG1(r9)
1339 std r5, VCPU_SPRG2(r9)
1340 std r6, VCPU_SPRG3(r9)
1443 std r7, VCORE_DPDES(r5)
1444 std r8, VCORE_VTB(r5)
1455 std r0, VCORE_TB_OFFSET_APPL(r5)
1619 4: std r4, VCPU_FAULT_DAR(r9)
1764 std r3,VCPU_GPR(R3)(r4)
2013 std r4,VCPU_DABR(r3)
2037 std r4, VCPU_DAWR0(r3)
2038 std r5, VCPU_DAWRX0(r3)
2055 std r11,VCPU_MSR(r3)
2065 std r0,VCPU_GPR(R3)(r3)
2100 std r14, VCPU_GPR(R14)(r3)
2101 std r15, VCPU_GPR(R15)(r3)
2102 std r16, VCPU_GPR(R16)(r3)
2103 std r17, VCPU_GPR(R17)(r3)
2104 std r18, VCPU_GPR(R18)(r3)
2105 std r19, VCPU_GPR(R19)(r3)
2106 std r20, VCPU_GPR(R20)(r3)
2107 std r21, VCPU_GPR(R21)(r3)
2108 std r22, VCPU_GPR(R22)(r3)
2109 std r23, VCPU_GPR(R23)(r3)
2110 std r24, VCPU_GPR(R24)(r3)
2111 std r25, VCPU_GPR(R25)(r3)
2112 std r26, VCPU_GPR(R26)(r3)
2113 std r27, VCPU_GPR(R27)(r3)
2114 std r28, VCPU_GPR(R28)(r3)
2115 std r29, VCPU_GPR(R29)(r3)
2116 std r30, VCPU_GPR(R30)(r3)
2117 std r31, VCPU_GPR(R31)(r3)
2154 std r3, VCPU_DEC_EXPIRES(r4)
2410 std r0, PPC_LR_STKOFF(r1)
2524 std r0, PPC_LR_STKOFF(r1)
2556 std r1, HSTATE_HOST_R1(r13)
2600 std r5, VCPU_TFHAR(r9)
2601 std r6, VCPU_TFIAR(r9)
2627 std r0, PPC_LR_STKOFF(r1)
2687 std r1, PACAR1(r13)
2690 std r9, 0(r1)
2691 std r0, GPR0(r1)
2692 std r9, GPR1(r1)
2693 std r2, GPR2(r1)
2697 std r0, _CCR(r1)
2698 std r12, _TRAP(r1)
2710 2: std r3, _NIP(r1)
2711 std r4, _MSR(r1)
2712 std r5, _DAR(r1)
2713 std r6, _DSISR(r1)
2718 std r0, GPR13(r1)
2721 std r5, ORIG_GPR3(r1)
2726 std r3, _LINK(r1)
2727 std r4, _CTR(r1)
2728 std r5, _XER(r1)
2729 std r6, SOFTE(r1)
2732 std r3, STACK_FRAME_OVERHEAD-16(r1)
2907 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
2912 std r4, VCPU_MMCR(r9)
2913 std r5, VCPU_MMCR + 8(r9)
2914 std r6, VCPU_MMCRA(r9)
2916 std r10, VCPU_MMCR + 16(r9)
2918 std r7, VCPU_SIAR(r9)
2919 std r8, VCPU_SDAR(r9)
2934 std r5, VCPU_SIER(r9)
2940 std r8, VCPU_MMCRS(r9)
2974 std r3, VCPU_CUR_ACTIVITY(r4)
2975 std r5, VCPU_ACTIVITY_START(r4)
2987 std r3, VCPU_CUR_ACTIVITY(r4)
2990 std r7, VCPU_ACTIVITY_START(r4)
2997 std r8, TAS_SEQCOUNT(r5)
3001 std r7, TAS_TOTAL(r5)
3007 3: std r3, TAS_MIN(r5)
3010 std r3, TAS_MAX(r5)
3013 std r8, TAS_SEQCOUNT(r5)