Lines Matching +full:no +full:- +full:read +full:- +full:rollover
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2005 MontaVista Software, Inc.
35 #include <asm/asm-offsets.h>
39 #include <asm/code-patching-asm.h>
47 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
48 * r4 - Starting address of the init RAM disk
49 * r5 - Ending address of the init RAM disk
50 * r6 - Start of kernel command line string (e.g. "mem=128")
51 * r7 - End of kernel command line string
75 addis r21,r21,(_stext - 0b)@ha
76 addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */
88 subf r3,r5,r6 /* r3 = r6 - r5 */
112 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
132 rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */
133 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
143 * virt_phys_offset = stext.run - kernstart_addr
151 * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
192 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
367 beq 2f /* Bail if no table */
383 /* Increment, rollover, and store TLB index */
395 /* Re-load the faulting address */
402 /* The bailout. Restore registers to pre-exception conditions
466 beq 2f /* Bail if no table */
482 /* Increment, rollover, and store TLB index */
494 /* Re-load the faulting address */
501 /* The bailout. Restore registers to pre-exception conditions
515 * r10 - EA of fault
516 * r11 - PTE high word value
517 * r12 - PTE low word value
518 * r13 - TLB index
519 * MMUCR - loaded with proper value when we get here
524 rlwimi r11,r12,0,0,31-PAGE_SHIFT
538 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
613 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
626 beq 2f /* Bail if no table */
643 2: /* The bailout. Restore registers to pre-exception conditions
700 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
713 beq 2f /* Bail if no table */
730 2: /* The bailout. Restore registers to pre-exception conditions
744 * r10 - free to use
745 * r11 - PTE high word value
746 * r12 - PTE low word value
747 * r13 - free to use
748 * MMUCR - loaded with proper value when we get here
753 rlwimi r11,r12,0,0,31-PAGE_SHIFT
758 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
857 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
889 /* Read the XLAT entry for our current mapping */
1015 addi r1,r1,1024-STACK_FRAME_OVERHEAD
1028 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1048 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
1123 /* Word 1 - use r25. RPN is the same as the original entry */
1180 /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
1212 * current 32-bit kernel code isn't too happy with icache != dcache
1232 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1236 * If the kernel was loaded at a non-zero 256 MB page, we need to