Lines Matching +full:0 +full:x8800
26 #size-cells = <0>;
28 PowerPC,8379@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x20000000>; // 512MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
55 ranges = <0 0x0 0xfe000000 0x02000000
56 1 0x0 0xf8000000 0x00008000
57 3 0x0 0xe0600000 0x00008000>;
59 flash@0,0 {
63 reg = <0 0x0 0x2000000>;
67 u-boot@0 {
68 reg = <0x0 0x100000>;
73 reg = <0x100000 0x800000>;
77 reg = <0x1d00000 0x200000>;
81 reg = <0x1f00000 0x100000>;
85 bcsr@1,0 {
86 reg = <1 0x0 0x8000>;
90 nand@3,0 {
95 reg = <3 0x0 0x8000>;
97 u-boot@0 {
98 reg = <0x0 0x100000>;
103 reg = <0x100000 0x300000>;
107 reg = <0x400000 0x1c00000>;
117 ranges = <0x0 0xe0000000 0x00100000>;
118 reg = <0xe0000000 0x00000200>;
119 bus-frequency = <0>;
123 reg = <0x200 0x100>;
130 sleep = <&pmc 0x0c000000>;
135 #size-cells = <0>;
136 cell-index = <0>;
138 reg = <0x3000 0x100>;
139 interrupts = <14 0x8>;
145 reg = <0x68>;
146 interrupts = <19 0x8>;
153 reg = <0x2e000 0x1000>;
154 interrupts = <42 0x8>;
158 clock-frequency = <0>;
164 #size-cells = <0>;
167 reg = <0x3100 0x100>;
168 interrupts = <15 0x8>;
174 cell-index = <0>;
176 reg = <0x7000 0x1000>;
177 interrupts = <16 0x8>;
186 reg = <0x82a8 4>;
187 ranges = <0 0x8100 0x1a8>;
190 cell-index = <0>;
191 dma-channel@0 {
193 reg = <0 0x80>;
194 cell-index = <0>;
200 reg = <0x80 0x80>;
207 reg = <0x100 0x80>;
214 reg = <0x180 0x28>;
223 reg = <0x23000 0x1000>;
225 #size-cells = <0>;
227 interrupts = <38 0x8>;
230 sleep = <&pmc 0x00c00000>;
236 cell-index = <0>;
240 reg = <0x24000 0x1000>;
241 ranges = <0x0 0x24000 0x1000>;
243 interrupts = <32 0x8 33 0x8 34 0x8>;
248 sleep = <&pmc 0xc0000000>;
253 #size-cells = <0>;
255 reg = <0x520 0x20>;
259 interrupts = <17 0x8>;
260 reg = <0x2>;
265 interrupts = <18 0x8>;
266 reg = <0x3>;
270 reg = <0x11>;
283 reg = <0x25000 0x1000>;
284 ranges = <0x0 0x25000 0x1000>;
286 interrupts = <35 0x8 36 0x8 37 0x8>;
291 sleep = <&pmc 0x30000000>;
296 #size-cells = <0>;
298 reg = <0x520 0x20>;
301 reg = <0x11>;
308 cell-index = <0>;
311 reg = <0x4500 0x100>;
312 clock-frequency = <0>;
313 interrupts = <9 0x8>;
321 reg = <0x4600 0x100>;
322 clock-frequency = <0>;
323 interrupts = <10 0x8>;
328 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
329 "fsl,sec2.1", "fsl,sec2.0";
330 reg = <0x30000 0x10000>;
331 interrupts = <11 0x8>;
335 fsl,exec-units-mask = <0x9fe>;
336 fsl,descriptor-types-mask = <0x3ab0ebf>;
337 sleep = <&pmc 0x03000000>;
342 reg = <0x18000 0x1000>;
343 interrupts = <44 0x8>;
345 sleep = <&pmc 0x000000c0>;
350 reg = <0x19000 0x1000>;
351 interrupts = <45 0x8>;
353 sleep = <&pmc 0x00000030>;
358 reg = <0x1a000 0x1000>;
359 interrupts = <46 0x8>;
361 sleep = <&pmc 0x0000000c>;
366 reg = <0x1b000 0x1000>;
367 interrupts = <47 0x8>;
369 sleep = <&pmc 0x00000003>;
381 #address-cells = <0>;
383 reg = <0x700 0x100>;
388 reg = <0xb00 0x100 0xa00 0x100>;
389 interrupts = <80 0x8>;
395 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
398 /* IDSEL 0x11 */
399 0x8800 0x0 0x0 0x1 &ipic 20 0x8
400 0x8800 0x0 0x0 0x2 &ipic 21 0x8
401 0x8800 0x0 0x0 0x3 &ipic 22 0x8
402 0x8800 0x0 0x0 0x4 &ipic 23 0x8
404 /* IDSEL 0x12 */
405 0x9000 0x0 0x0 0x1 &ipic 22 0x8
406 0x9000 0x0 0x0 0x2 &ipic 23 0x8
407 0x9000 0x0 0x0 0x3 &ipic 20 0x8
408 0x9000 0x0 0x0 0x4 &ipic 21 0x8
410 /* IDSEL 0x13 */
411 0x9800 0x0 0x0 0x1 &ipic 23 0x8
412 0x9800 0x0 0x0 0x2 &ipic 20 0x8
413 0x9800 0x0 0x0 0x3 &ipic 21 0x8
414 0x9800 0x0 0x0 0x4 &ipic 22 0x8
416 /* IDSEL 0x15 */
417 0xa800 0x0 0x0 0x1 &ipic 20 0x8
418 0xa800 0x0 0x0 0x2 &ipic 21 0x8
419 0xa800 0x0 0x0 0x3 &ipic 22 0x8
420 0xa800 0x0 0x0 0x4 &ipic 23 0x8
422 /* IDSEL 0x16 */
423 0xb000 0x0 0x0 0x1 &ipic 23 0x8
424 0xb000 0x0 0x0 0x2 &ipic 20 0x8
425 0xb000 0x0 0x0 0x3 &ipic 21 0x8
426 0xb000 0x0 0x0 0x4 &ipic 22 0x8
428 /* IDSEL 0x17 */
429 0xb800 0x0 0x0 0x1 &ipic 22 0x8
430 0xb800 0x0 0x0 0x2 &ipic 23 0x8
431 0xb800 0x0 0x0 0x3 &ipic 20 0x8
432 0xb800 0x0 0x0 0x4 &ipic 21 0x8
434 /* IDSEL 0x18 */
435 0xc000 0x0 0x0 0x1 &ipic 21 0x8
436 0xc000 0x0 0x0 0x2 &ipic 22 0x8
437 0xc000 0x0 0x0 0x3 &ipic 23 0x8
438 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
440 interrupts = <66 0x8>;
441 bus-range = <0x0 0x0>;
442 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
443 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
444 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
445 sleep = <&pmc 0x00010000>;
446 clock-frequency = <0>;
450 reg = <0xe0008500 0x100 /* internal registers */
451 0xe0008300 0x8>; /* config space access registers */