Lines Matching +full:0 +full:x8800
28 #size-cells = <0>;
30 PowerPC,8378@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
58 1 0x0 0xf8000000 0x00008000
59 3 0x0 0xe0600000 0x00008000>;
61 flash@0,0 {
65 reg = <0 0x0 0x2000000>;
69 u-boot@0 {
70 reg = <0x0 0x100000>;
75 reg = <0x100000 0x800000>;
79 reg = <0x1d00000 0x200000>;
83 reg = <0x1f00000 0x100000>;
87 bcsr@1,0 {
88 reg = <1 0x0 0x8000>;
92 nand@3,0 {
97 reg = <3 0x0 0x8000>;
99 u-boot@0 {
100 reg = <0x0 0x100000>;
105 reg = <0x100000 0x300000>;
109 reg = <0x400000 0x1c00000>;
119 ranges = <0x0 0xe0000000 0x00100000>;
120 reg = <0xe0000000 0x00000200>;
121 bus-frequency = <0>;
125 reg = <0x200 0x100>;
132 sleep = <&pmc 0x0c000000>;
137 #size-cells = <0>;
138 cell-index = <0>;
140 reg = <0x3000 0x100>;
141 interrupts = <14 0x8>;
147 reg = <0x68>;
148 interrupts = <19 0x8>;
155 reg = <0x2e000 0x1000>;
156 interrupts = <42 0x8>;
160 clock-frequency = <0>;
166 #size-cells = <0>;
169 reg = <0x3100 0x100>;
170 interrupts = <15 0x8>;
176 cell-index = <0>;
178 reg = <0x7000 0x1000>;
179 interrupts = <16 0x8>;
188 reg = <0x82a8 4>;
189 ranges = <0 0x8100 0x1a8>;
192 cell-index = <0>;
193 dma-channel@0 {
195 reg = <0 0x80>;
196 cell-index = <0>;
202 reg = <0x80 0x80>;
209 reg = <0x100 0x80>;
216 reg = <0x180 0x28>;
225 reg = <0x23000 0x1000>;
227 #size-cells = <0>;
229 interrupts = <38 0x8>;
232 sleep = <&pmc 0x00c00000>;
238 cell-index = <0>;
242 reg = <0x24000 0x1000>;
243 ranges = <0x0 0x24000 0x1000>;
245 interrupts = <32 0x8 33 0x8 34 0x8>;
250 sleep = <&pmc 0xc0000000>;
255 #size-cells = <0>;
257 reg = <0x520 0x20>;
261 interrupts = <17 0x8>;
262 reg = <0x2>;
267 interrupts = <18 0x8>;
268 reg = <0x3>;
272 reg = <0x11>;
285 reg = <0x25000 0x1000>;
286 ranges = <0x0 0x25000 0x1000>;
288 interrupts = <35 0x8 36 0x8 37 0x8>;
293 sleep = <&pmc 0x30000000>;
298 #size-cells = <0>;
300 reg = <0x520 0x20>;
303 reg = <0x11>;
310 cell-index = <0>;
313 reg = <0x4500 0x100>;
314 clock-frequency = <0>;
315 interrupts = <9 0x8>;
323 reg = <0x4600 0x100>;
324 clock-frequency = <0>;
325 interrupts = <10 0x8>;
330 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
331 "fsl,sec2.1", "fsl,sec2.0";
332 reg = <0x30000 0x10000>;
333 interrupts = <11 0x8>;
337 fsl,exec-units-mask = <0x9fe>;
338 fsl,descriptor-types-mask = <0x3ab0ebf>;
339 sleep = <&pmc 0x03000000>;
351 #address-cells = <0>;
353 reg = <0x700 0x100>;
358 reg = <0xb00 0x100 0xa00 0x100>;
359 interrupts = <80 0x8>;
365 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
368 /* IDSEL 0x11 */
369 0x8800 0x0 0x0 0x1 &ipic 20 0x8
370 0x8800 0x0 0x0 0x2 &ipic 21 0x8
371 0x8800 0x0 0x0 0x3 &ipic 22 0x8
372 0x8800 0x0 0x0 0x4 &ipic 23 0x8
374 /* IDSEL 0x12 */
375 0x9000 0x0 0x0 0x1 &ipic 22 0x8
376 0x9000 0x0 0x0 0x2 &ipic 23 0x8
377 0x9000 0x0 0x0 0x3 &ipic 20 0x8
378 0x9000 0x0 0x0 0x4 &ipic 21 0x8
380 /* IDSEL 0x13 */
381 0x9800 0x0 0x0 0x1 &ipic 23 0x8
382 0x9800 0x0 0x0 0x2 &ipic 20 0x8
383 0x9800 0x0 0x0 0x3 &ipic 21 0x8
384 0x9800 0x0 0x0 0x4 &ipic 22 0x8
386 /* IDSEL 0x15 */
387 0xa800 0x0 0x0 0x1 &ipic 20 0x8
388 0xa800 0x0 0x0 0x2 &ipic 21 0x8
389 0xa800 0x0 0x0 0x3 &ipic 22 0x8
390 0xa800 0x0 0x0 0x4 &ipic 23 0x8
392 /* IDSEL 0x16 */
393 0xb000 0x0 0x0 0x1 &ipic 23 0x8
394 0xb000 0x0 0x0 0x2 &ipic 20 0x8
395 0xb000 0x0 0x0 0x3 &ipic 21 0x8
396 0xb000 0x0 0x0 0x4 &ipic 22 0x8
398 /* IDSEL 0x17 */
399 0xb800 0x0 0x0 0x1 &ipic 22 0x8
400 0xb800 0x0 0x0 0x2 &ipic 23 0x8
401 0xb800 0x0 0x0 0x3 &ipic 20 0x8
402 0xb800 0x0 0x0 0x4 &ipic 21 0x8
404 /* IDSEL 0x18 */
405 0xc000 0x0 0x0 0x1 &ipic 21 0x8
406 0xc000 0x0 0x0 0x2 &ipic 22 0x8
407 0xc000 0x0 0x0 0x3 &ipic 23 0x8
408 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
410 interrupts = <66 0x8>;
411 bus-range = <0x0 0x0>;
412 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
413 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
414 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
415 clock-frequency = <0>;
416 sleep = <&pmc 0x00010000>;
420 reg = <0xe0008500 0x100 /* internal registers */
421 0xe0008300 0x8>; /* config space access registers */
432 reg = <0xe0009000 0x00001000>;
433 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
434 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
435 bus-range = <0 255>;
436 interrupt-map-mask = <0xf800 0 0 7>;
437 interrupt-map = <0 0 0 1 &ipic 1 8
438 0 0 0 2 &ipic 1 8
439 0 0 0 3 &ipic 1 8
440 0 0 0 4 &ipic 1 8>;
441 sleep = <&pmc 0x00300000>;
442 clock-frequency = <0>;
444 pcie@0 {
448 reg = <0 0 0 0 0>;
449 ranges = <0x02000000 0 0xa8000000
450 0x02000000 0 0xa8000000
451 0 0x10000000
452 0x01000000 0 0x00000000
453 0x01000000 0 0x00000000
454 0 0x00800000>;
464 reg = <0xe000a000 0x00001000>;
465 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
466 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
467 bus-range = <0 255>;
468 interrupt-map-mask = <0xf800 0 0 7>;
469 interrupt-map = <0 0 0 1 &ipic 2 8
470 0 0 0 2 &ipic 2 8
471 0 0 0 3 &ipic 2 8
472 0 0 0 4 &ipic 2 8>;
473 sleep = <&pmc 0x000c0000>;
474 clock-frequency = <0>;
476 pcie@0 {
480 reg = <0 0 0 0 0>;
481 ranges = <0x02000000 0 0xc8000000
482 0x02000000 0 0xc8000000
483 0 0x10000000
484 0x01000000 0 0x00000000
485 0x01000000 0 0x00000000
486 0 0x00800000>;